OR3C80 datasheet(20/210 Pages) AGERE

20 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Programmable Logic Cells (continued)

Data is written to the write data, write address, and

write enable registers on the active edge of the clock,

but data is not written into the RAM until the next clock

edge one-half cycle later. The read port is actually

asynchronous, providing the user with read data very

quickly after setting the read address, but timing is also

provided so that the read port may be treated as fully

synchronous for write then read applications. If the

read and write address lines are tied together (main-

taining MSB to MSB, etc.), then the dual-port RAM

operates as a synchronous single-port RAM. If the

write enable is disabled, and an initial memory contents

is provided at configuration time, the memory acts as a

ROM (the write data and write address ports and write

port enables are not used).

Wider memories can be created by operating two or

more memory mode PFUs in parallel, all with the same

address and control signals, but each with a different

nibble of data. To increase memory word depth above

32, two or more PLCs can be used. Figure 10 shows a

128 x 8 dual-port RAM that is implemented in eight

PLCs. This figure demonstrates data path width expan-

sion by placing two memories in parallel to achieve an

8-bit data path. Depth expansion is applied to achieve

128 words deep using the 32-word deep PFU memo-

ries. In addition to the PFU in each PLC, the SLIC

(described in the next section) in each PLC is used for

read address decodes and 3-state drivers. The 128 x 8

RAM shown could be made to operate as a single-port

RAM by tying (bit-for-bit) the read and write addresses.

To achieve depth expansion, one or two of the write

address bits (generally the MSBs) are routed to the

write port enables as in Figure 10. For 2 bits, the bits

select which 32-word bank of RAM of the four available

from a decode of two WPE inputs is to be written. Simi-

larly, 2 bits of the read address are decoded in the

SLIC and are used to control the 3-state buffers

through which the read data passes. The write data

bus is common, with separate nibbles for width expan-

sion, across all PLCs, and the read data bus is com-

mon (again, with separate nibbles) to all PLCs at the

output of the 3-state buffers.

Figure 10 also shows a new optional capability to pro-

vide a read enable for RAMs/ROMs in Series 3 using

the SLIC cell. The read enable will 3-state the read

data bus when inactive, allowing the write data and

read data buses to be tied together if desired.

Figure 10. Memory Mode Expansion Example—128 x 8 RAM

5-5749(F)

RD[7:0]

WA[6:0]

RA[6:0]

CLK

WPE0

WPE1

WD[7:4]

PLC

WD[7:0]

WPE0

WPE1

RD[3:0]

WD[3:0]

PLC

RD[7:4]

WPE0

WPE1

WD[7:4]

PLC

WPE0

WPE1

RD[3:0]

WD[3:0]

PLC

RD[7:4]

PFU

SLIC

OR3C80 Datasheet(PDF) 20 Page - Agere Systems

OR3C80 Datasheet(HTML) 20 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL