OR3C80 datasheet(43/210 Pages) AGERE

43 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Programmable Input/Output Cells

(continued)

PIO Logic Function Generator

The PIO logic block can also generate logic functions

based on the signals on the OUT2 and CLK ports of

the PIO. The functions are AND, NAND, OR, NOR,

XOR, and XNOR. Table 10 is provided as a summary

of the PIO logic options.

PIO Register Control Signals

As discussed in the Inputs and Outputs subsections,

the PIO latches/FFs have various clock, clock enable

(CE), local set/reset (LSR), and global set/reset

(GSRN) controls. Table 11 provides a summary of

these control signals and their effect on the PIO

latches/FFs. Note that all control signals are optionally

invertible.

Table 10. PIO Logic Options

Option

Description

OUT1OUTREG

Data at OUT1 output when clock

low, data at FF out when clock

high.

OUT2OUTREG

Data at OUT2 output when clock

low, data at FF out when clock

high.

OUT1OUT2

Data at OUT1 output when clock

low, data at OUT2 when clock

high.

AND

Output logical AND of signals on

OUT2 and clock.

NAND

Output logical NAND of signals

on OUT2 and clock.

Output logical OR of signals on

OUT2 and clock.

NOR

Output logical NOR of signals on

OUT2 and clock.

XOR

Output logical XOR of signals on

OUT2 and clock.

XNOR

Output logical XNOR of signals

on OUT2 and clock.

Table 11. PIO Register Control Signals

Control Signal

Effect/Functionality

ExpressCLK

Clocks input fast-capture latch;

optionally clocks output FF, or

3-state FF.

System Clock

(SCLK)

Clocks input latch/FF; optionally

clocks output FF, or 3-state FF.

Clock Enable

(CE)

Optionally enables/disables input

FF (not available for input latch

mode); optionally enables/dis-

ables output FF; separate CE

inversion capability for input and

output.

Local Set/Reset

(LSR)

Option to disable; affects input

latch/FF, output FF, and 3-state

FF if enabled.

Global Set/Reset

(GSRN)

Option to enable or disable per

PIO after initial configuration.

Set/Reset Mode

The input latch/FF, output FF, and

3-state FF are individually set or

reset by both the LSR and GSRN

inputs.

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