ADSP-BF607 datasheet(52/112 Pages) AD

52 / 112 page

Rev. 0

Page 52 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

SPECIFICATIONS

For information about product specifications please contact

your ADI representative.

OPERATING CONDITIONS

Parameter

Conditions

Min

Nominal

Max

Unit

VDD_INT

Internal Supply Voltage

CCLK ≤ 500 MHz

1.19

1.25

1.32

VDD_EXT

1 Must remain powered (even if the associated function is not used).

External Supply Voltage

1.7

1.8

1.9

VDD_EXT

External Supply Voltage

3.13

3.3

3.47

VDD_DMC

DDR2/LPDDR Supply Voltage

1.7

1.8

1.9

VDD_USB

2 If not used, connect to 1.8 V or 3.3 V.

USB Supply Voltage

3.13

3.3

3.47

VDD_TD

Thermal Diode Supply Voltage

3.13

3.3

3.47

VIH

3 Parameter value applies to all input and bidirectional signals except TWI signals, DMC0 signals and USB0 signals.

High Level Input Voltage

VDD_EXT = 3.47 V

2.1

VIH

High Level Input Voltage

VDD_EXT = 1.9 V

0.7 × VDD_EXT

VIHTWI

4, 5

4 Parameter applies to TWI signals.

5 TWI signals are pulled up to VBUSTWI. See Table 16.

High Level Input Voltage

VDD_EXT = Maximum

0.7 × VVBUSTWI

VVBUSTWI

VIH_DDR2

6, 7

6 Parameter applies to DMC0 signals in DDR2 mode.

7 VDDR_REF is the voltage applied to pin VREF_DMC, nominally VDD_DMC/2.

VDD_DMC = 1.9 V

VDDR_REF + 0.25

VIH_LPDDR

8 Parameter applies to DMC0 signals in LPDDR mode.

VDD_DMC = 1.9 V

0.8 × VDD_DMC

VID_DDR2

9 Parameter applies to signals DMC0_CK, DMC0_CK, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS when used in DDR2 differential input mode.

Differential Input Voltage

VIX = 1.075 V

0.50

VID_DDR2

Differential Input Voltage

VIX = 0.725 V

0.55

VIL

Low Level Input Voltage

VDD_EXT = 3.13 V

0.8

VIL

Low Level Input Voltage

VDD_EXT = 1.7 V

0.3 × VDD_EXT

VILTWI

4, 5

Low Level Input Voltage

VDD_EXT = Minimum

0.3 × VVBUSTWI

VIL_DDR2

6, 7

VDD_DMC = 1.7 V

VDDR_REF – 0.25

VIL_LPDDR

VDD_DMC = 1.7 V

0.2 × VDD_DMC

Junction Temperature

TAMBIENT = –40°C to +85°C

–40

+105

°C

Junction Temperature

TAMBIENT = –40°C to +105°C

–40

+125

°C

Table 16. TWI_VSEL Selections and VDD_EXT/VBUSTWI

VDD_EXT Nominal

VBUSTWI Min

VBUSTWI Nom

VBUSTWI Max

Unit

TWI0001

1 Designs must comply with the VDD_EXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.

3.300

3.135

3.300

3.465

TWI001

1.800

1.700

1.800

1.900

TWI011

1.800

3.135

3.300

3.465

TWI100

3.300

4.750

5.000

5.250

ADSP-BF607 Datasheet(PDF) 52 Page - Analog Devices

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