ADSP-BF607 datasheet(76/112 Pages) AD

76 / 112 page

Rev. 0

Page 76 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

Table 45. Link Ports—Transmit

VDD_EXT

1.8V Nominal/3.3V Nominal

Parameter

Min

Max

Unit

Timing Requirements

tSLACH

LP_ACK Setup Before LP_CLK Low

2 × tSCLK0 + 10

tHLACH

LP_ACK Hold After LP_CLK Low

Switching Characteristics

tDLDCH

Data Delay After LP_CLK High

2.5

tHLDCH

Data Hold After LP_CLK High

–1

tLCLKTWL

LP_CLK Width Low

0.4 × tLCLK

0.6 × tLCLK

tLCLKTWH

LP_CLK Width High

0.4 × tLCLK

0.6 × tLCLK

tDLACLK

LP_CLK Low Delay After LP_ACK High

tSCLK0 + 4

(2 × tSCLK0) + tLCLK + 10

Figure 30. Link Ports—Transmit

LP_CLK

LP_Dx

(DATA)

LP_ACK (IN)

OUT

tDLDCH

tHLDCH

tSLACH

tHLACH

tDLACLK

tLCLKTWH

tLCLKTWL

LAST BYTE

TRANSMITTED

FIRST BYTE

TRANSMITTED

NOTES

The t

SLACH and tHLACH

specifications apply only to the LP_ACK falling edge. If these specifications are met,

LP_CLK would extend and the dotted LP_CLK falling edge would not occur as shown. The position of the

dotted falling edge can be calculated using the t

LCLKTWH specification.

LCLKTWH Min should be used for t SLACH

and t

LCLKTWH Max for tHLACH.

ADSP-BF607 Datasheet(PDF) 76 Page - Analog Devices

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