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ADSP-BF607 Datasheet(PDF) 77 Page - Analog Devices

Part # ADSP-BF607
Description  Blackfin Dual Core Embedded Processor
PDF  112 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF607 Datasheet(HTML) 77 Page - Analog Devices

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Rev. 0
|
Page 77 of 112
|
June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) serial clock 
(SPT_CLK) width. In Figure 31 either the rising edge or the fall-
ing edge of SPT_CLK (external or internal) can be used as the
active sampling edge.
Table 46. Serial Ports—External Clock
VDD_EXT
1.8V Nominal
VDD_EXT
3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSFSE
Frame Sync Setup Before SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)1
22
ns
tHFSE
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)
1
2.7
2.7
ns
tSDRE
Receive Data Setup Before Receive SPT_CLK
1
22
ns
tHDRE
Receive Data Hold After SPT_CLK1
2.7
2.7
ns
tSCLKW
SPT_CLK Width for External SPT_CLK Data/FS
Receive
2
[0.5 × tSCLK1 – 0.5] or [5.5]
[0.5 × tSCLK1 – 0.5] or [5.5]
ns
SPT_CLK Width for External SPT_CLK Data/FS
Transmit
2
[0.5 × tSCLK1 – 0.5] or [8]
[0.5 × tSCLK1 – 0.5] or [8]
ns
tSPTCLK
SPT_CLK Period for External SPT_CLK Data/FS
Receive
2
[tSCLK1 – 1] or [12]
[tSCLK1 – 1] or [12]
ns
SPT_CLK Period for External SPT_CLK Data/FS
Transmit2
[tSCLK1 – 1] or [17]
[tSCLK1 – 1] or [17]
ns
Switching Characteristics
tDFSE
Frame Sync Delay After SPT_CLK
(Internally Generated Frame Sync in either
Transmit or Receive Mode)
3
19.3
14.5
ns
tHOFSE
Frame Sync Hold After SPT_CLK
(Internally Generated Frame Sync in either
Transmit or Receive Mode)3
22
ns
tDDTE
Transmit Data Delay After Transmit SPT_CLK
3
18.8
14
ns
tHDTE
Transmit Data Hold After Transmit SPT_CLK
3
22
ns
1 Referenced to sample edge.
2 Whichever is greater.
3 Referenced to drive edge.



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