ADSP-BF607 datasheet(98/112 Pages) AD

98 / 112 page

Rev. 0

Page 98 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

JTAG Test And Emulation Port Timing

Table 67 and Figure 53 describe JTAG port operations.

Table 67. JTAG Port Timing

Parameter

VDD_EXT

1.8V Nominal

VDD_EXT

3.3V Nominal

Min

Max

Min

Max

Unit

Timing Requirements

tTCK

JTG_TCK Period

tSTAP

JTG_TDI, JTG_TMS Setup Before JTG_TCK High

tHTAP

JTG_TDI, JTG_TMS Hold After JTG_TCK High

tSSYS

System Inputs Setup Before JTG_TCK High1

tHSYS

System Inputs Hold After JTG_TCK High

tTRSTW

JTG_TRST Pulse Width (measured in JTG_TCK cycles)2

44TCK

Switching Characteristics

tDTDO

JTG_TDO Delay from JTG_TCK Low

13.5

tDSYS

System Outputs Delay After JTG_TCK Low

1 System Inputs = DMC0_DQ00–15, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, PA_15–0, PB_15–0, PC_15–0, PD_15–0, PE_15–0, PF_15–0, PG_15–0,

SMC0_ARDY_NORWT, SMC0_BR, SMC0_D15–0, SYS_BMODE0–2, SYS_HWRST, SYS_FAULT, SYS_FAULT, SYS_NMI_RESOUT, SYS_PWRGD, TWI0_SCL, TWI0_

SDA, TWI1_SCL, TWI1_SDA.

2 50 MHz Maximum.

3 System Outputs = DMC0_A00–13, DMC0_BA0–2, DMC0_CAS, DMC0_CK, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQ00–15, DMC0_LDM, DMC0_LDQS,

DMC0_LDQS, DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, DMC0_WE, JTG_EMU, PA_15–0, PB_15–0, PC_15–0, PD_15–0, PE_15–0, PF_

15–0, PG_15–0, SMC0_AMS0, SMC0_AOE_NORDV, SMC0_ARE, SMC0_AWE, SMC0_A01, SMC0_A02, SMC0_D15–0, SYS_CLKOUT, SYS_FAULT, SYS_FAULT,

SYS_NMI_RESOUT, TWI0_SCL, TWI0_SDA, TWI1_SCL, TWI1_SDA.

Figure 53. JTAG Port Timing

JTG_TCK

JTG_TMS

JTG_TDI

JTG_TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP

tHTAP

tDTDO

tSSYS

tHSYS

tDSYS

ADSP-BF607 Datasheet(PDF) 98 Page - Analog Devices

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