ADSP-BF607 datasheet(55/112 Pages) AD

55 / 112 page

Rev. 0

Page 55 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

IDD_IDLE

VDD_INT Current in Idle

fCCLK = 500 MHz

ASFC0 = 0.14 (Idle)

ASFC1 = 0 (Disabled)

fSYSCLK = 250 MHz, fSCLK0/1 = 125 MHz

fDCLK = 0 MHz (DDR Disabled)

fUSBCLK = 0 MHz (USB Disabled)

No PVP or DMA activity

TJ = 25°C

137

IDD_TYP

VDD_INT Current

fCCLK = 500 MHz

ASFC0 = 1.0 (Full-on Typical)

ASFC1 = 0.86 (App)

fSYSCLK = 250 MHz, fSCLK0/1 = 125 MHz

fDCLK = 250 MHz

fUSBCLK = 0 MHz (USB Disabled)

DMA Data Rate = 124 MB/s

Medium PVP Activity

TJ = 25°C

357

IDD_HIBERNATE

22, 24 Hibernate State Current

VDD_INT = 0 V,

VDD_EXT = VDD_TD = VDD_USB = 3.3 V,

VDD_DMC = 1.8 V, VREF_DMC = 0.9 V,

TJ = 25°C, fCLKIN = 0 MHz

A

IDD_HIBERNATE

22, 24 Hibernate State Current

Without USB

VDD_INT = 0 V,

VDD_EXT = VDD_TD = VDD_USB = 3.3 V,

VDD_DMC = 1.8 V, VREF_DMC = 0.9 V,

TJ = 25°C,

fCLKIN = 0 MHz, USB protection

disabled (USB0_PHY_CTL.DIS=1)

A

IDD_INT

VDD_INT Current

fCCLK > 0 MHz

fSCLK0/1 ≥ 0 MHz

See IDDINT_TOT

equation

on Page 56

1 Applies to all output and bidirectional signals except DMC0 signals, TWI signals and USB0 signals.

2 Applies to all DMC0 output and bidirectional signals in DDR2 full drive strength mode.

3 Applies to all DMC0 output and bidirectional signals in DDR2 half drive strength mode.

4 Applies to all DMC0 output and bidirectional signals in LPDDR full drive strength mode.

5 Applies to all DMC0 output and bidirectional signals in LPDDR three-quarter drive strength mode.

6 Applies to all DMC0 output and bidirectional signals in LPDDR half drive strength mode.

7 Applies to all DMC0 output and bidirectional signals in LPDDR one-quarter drive strength mode.

8 Applies to all output and bidirectional signals except DMC0 signals and USB0 signals.

9 Applies to signals SMC0_ARDY, SMC0_BR, SYS_BMODE0–2, SYS_CLKIN, SYS_HWRST, SYS_PWRGD, JTG_TDI, and JTG_TMS.

10Applies to signals JTG_TCK and JTG_TRST.

11Applies to signals SMC0_ARDY, SMC0_BR, SYS_BMODE0–2, SYS_CLKIN, SYS_HWRST, SYS_PWRGD, JTG_TCK, and JTG_TRST.

12Applies to signals JTG_TDI, JTG_TMS.

13Applies to signal USB0_CLKIN.

14Applies to signals PA0–15, PB0–15, PC0–15, PD0–15, PE0–15, PF0–15, PG0–15, SMC0_AMS0, SMC0_ARE, SMC0_AWE, SMC0_A0E, SMC0_A01–02, SMC0_D00–15, SYS_

FAULT, SYS_FAULT, JTG_EMU, JTG_TDO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS.

15 Applies to DMC0_A[00:13], DMC0_BA[0:2], DMC0_CAS, DMC0_CS0, DMC0_DQ[00:15], DMC0_LQDS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM,

DMC0_UDM, DMC0_ODT, DMC0_RAS, and DMC0_WE.

16Applies to signals PA0–15, PB0–15, PC0–15, PD0–15, PE0–15, PF0–15, PG0–15, SMC0_A0E, SMC0_A01–02, SMC0_D00–15, SYS_FAULT, SYS_FAULT, JTG_EMU, JTG_

TDO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS, DMC0_A00–13, DMC0_BA0–2, DMC0_CAS, DMC0_CS0, DMC0_DQ00–15, DMC0_LQDS, DMC0_

LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM, DMC0_UDM, DMC0_ODT, DMC0_RAS, DMC0_WE, and TWI signals.

17Applies to signals SMC0_AMS0, SMC0_ARE, SMC0_AWE, and when RSI pull-up resistors are enabled, PE10–13, 15 and PG00, 02, 03, 05.

18Applies to all TWI signals.

19Applies to all signals, except DMC0 and TWI signals.

20Guaranteed, but not tested.

21Applies to all DMC0 signals

22See the ADSP-BF60x Blackfin Processor Hardware Reference Manual for definition of deep sleep and hibernate operating modes.

23Additional information can be found at Total Internal Power Dissipation on Page 56.

24Applies to VDD_EXT, VDD_DMC, VDD_USB and VDD_TD supply signals only. Clock inputs are tied high or low.

Parameter

Test Conditions

Min

Typical

Max

Unit

ADSP-BF607 Datasheet(PDF) 55 Page - Analog Devices

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