ADSP-BF607 datasheet(89/112 Pages) AD

89 / 112 page

Rev. 0

Page 89 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

Serial Peripheral Interface (SPI) Port—SPI_RDY Timing

Table 56. SPI Port—SPI_RDY Timing

VDD_EXT

1.8 V/3.3 V Nominal

Parameter

Min

Max

Unit

Timing Requirements

tSRDYSCKM0 Minimum Setup Time for SPI_RDY De-assertion in Master

Mode Before Last SPI_CLK Edge of Valid Data Transfer to



Block Subsequent Transfer with CPHA = 0

(2.5 + 1.5 × BAUD

1) × t

SCLK1 +

17.5

tSRDYSCKM1 Minimum Setup Time for SPI_RDY De-assertion in Master

Mode Before Last SPI_CLK Edge of Valid Data Transfer to



Block Subsequent Transfer with CPHA = 1

(1.5 × BAUD1) × tSCLK1 + 17.5

Switching Characteristic

tSRDYSCKM

Time Between Assertion of SPI_RDY by Slave and First Edge



of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD = 0

(STOP, LEAD, LAG = 0)

3 × tSCLK1

4 × tSCLK1 + 17.5

Time Between Assertion of SPI_RDY by Slave and First Edge



of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD ≥ 1

(STOP, LEAD, LAG = 0)

(4 + 1.5 × BAUD

1) × t

SCLK1

(5 + 1.5 × BAUD

1) × t

SCLK1 +

17.5

Time Between Assertion of SPI_RDY by Slave and First Edge



of SPI_CLK for New SPI Transfer with CPHA = 1 (STOP, LEAD,



LAG = 0)

(3 + 0.5 × BAUD1) × tSCLK1

(4 + 0.5 × BAUD1) × tSCLK1 +

17.5

1 BAUD value set using the SPI_CLK.BAUD bits.

Figure 41. SPI_RDY Setup Before SPI_CLK with CPHA = 0

Figure 42. SPI_RDY Setup Before SPI_CLK with CPHA = 1

SPI_CLK

(CPOL = 0)

SPI_CLK

(CPOL = 1)

tSRDYSCKM0

SPI_RDY

SPI_CLK

(CPOL = 0)

SPI_CLK

(CPOL = 1)

tSRDYSCKM1

SPI_RDY

ADSP-BF607 Datasheet(PDF) 89 Page - Analog Devices

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