ADSP-BF607 datasheet(75/112 Pages) AD

75 / 112 page

Rev. 0

Page 75 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

Link Ports

Calculation of link receiver data setup and hold relative to link

clock is required to determine the maximum allowable skew

that can be introduced in the transmission path length differ-

ence between LP_Dx (data) and LP_CLK. Setup skew is the

maximum delay that can be introduced in LP_Dx relative to

LP_CLK:

(setup skew = tLCLKTWH min – tDLDCH – tSLDCL). Hold skew is the

maximum delay that can be introduced in LP_CLK relative to

LP_Dx: (hold skew = tLCLKTWL min – tHLDCH – tHLDCL).

Table 44. Link Ports—Receive

VDD_EXT

1.8V Nominal/3.3V Nominal

Parameter

Min

Max

Unit

Timing Requirements

tSLDCL

Data Setup Before LP_CLK Low

tHLDCL

Data Hold After LP_CLK Low

tLCLKIW

LP_CLK Period

[tSCLK0 – 1] or [12]

tLCLKRWL

LP_CLK Width Low

[0.5 × tSCLK0 – 0.5] or [5.5]

tLCLKRWH

LP_CLK Width High

[0.5 × tSCLK0 – 0.5] or [5.5]

Switching Characteristic

tDLALC

LP_ACK Low Delay After LP_CLK Low2

1.5 × tSCLK0 + 4

2.5 × tSCLK0 + 12

1 Whichever is greater.

2 LP_ACK goes low with tDLALC relative to rise of LP_CLK after first byte, but does not go low if the receiver's link buffer is not about to fill.

Figure 29. Link Ports—Receive

LP_D7–0

LP_CLK

LP_ACK (OUT)

tHLDCL

tSLDCL

tLCLKRWH

tLCLKRWL

tLCLKIW

tDLALC

ADSP-BF607 Datasheet(PDF) 75 Page - Analog Devices

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