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ADSP-BF607 Datasheet(PDF) 74 Page - Analog Devices |
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ADSP-BF607 Datasheet(HTML) 74 Page - Analog Devices |
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74 / 112 page  Rev. 0 | Page 74 of 112 | June 2013 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 43. Enhanced Parallel Peripheral Interface—External Clock VDD_EXT 1.8V Nominal VDD_EXT 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements tPCLKW EPPI_CLK Width for Data Transmit, FS External Data/FS Receive 1 [0.5 × tSCLK0 – 0.5] or [5.5] [0.5 × tSCLK0 – 0.5] or [5.5] ns EPPI_CLK Width for Data Transmit, FS Internal Data/FS Transmit1 [0.5 × tSCLK0 – 1] or [7.5] [0.5 × tSCLK0 – 1] or [7.5] ns tPCLK EPPI_CLK Period for Data Receive, FS External Data/FS Receive1 [tSCLK0 – 1] or [12] [tSCLK0 – 1] or [12] ns EPPI_CLK Period for Data Receive, FS Internal Data/FS Transmit1 [tSCLK0 – 1] or [17] [tSCLK0 – 1] or [17] ns tSFSPE External Frame Sync Setup Before EPPI_CLK 2 2 ns tHFSPE External Frame Sync Hold After EPPI_CLK 3.7 3.7 ns tSDRPE Receive Data Setup Before EPPI_CLK 2 2 ns tHDRPE Receive Data Hold After EPPI_CLK 3.7 3.7 ns Switching Characteristics tDFSPE Internal Frame Sync Delay After EPPI_CLK 20.1 15.3 ns tHOFSPE Internal Frame Sync Hold After EPPI_CLK 2.4 2.4 ns tDDTPE Transmit Data Delay After EPPI_CLK 20.1 15.3 ns tHDTPE Transmit Data Hold After EPPI_CLK 2.4 2.4 ns 1 Whichever is greater. Figure 27. PPI GP Receive Mode with External Frame Sync Timing Figure 28. PPI GP Transmit Mode with External Frame Sync Timing tPCLK tSFSPE DATA SAMPLED / FRAME SYNC SAMPLED DATA SAMPLED / FRAME SYNC SAMPLED EPPI_D00-23 EPPI_CLK EPPI_FS1/2 tHFSPE tHDRPE tSDRPE tPCLKW tHDTPE tSFSPE DATA DRIVEN / FRAME SYNC SAMPLED tHFSPE tDDTPE tPCLK tPCLKW EPPI_D00-23 EPPI_CLK EPPI_FS1/2 |
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