ADSP-BF607 datasheet(93/112 Pages) AD

93 / 112 page

Rev. 0

Page 93 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

ADC Controller Module (ACM) Timing

Table 61 and Figure 48 describe ACM operations.

Note that the ACM clock (ACMx_CLK) frequency in MHz is

set by the following equation where CKDIV is a field in the

ACM_TC0 register and ranges from 1 to 255. Setup cycles (SC)

in Table 61 is also a field in the ACM_TC0 register and ranges

from 0 to 4095. Hold Cycles (HC) is a field in the ACM_TC1

ACLK

fSCLK1

CKDIV

---------------------------

ACLK

-----------------

Table 61. ACM Timing

VDD_EXT

1.8 V/3.3V Nominal

Parameter

Min

Max

Unit

Timing Requirements

tSDR

SPORT DRxPRI/DRxSEC Setup Before ACMx_CLK

tHDR

SPORT DRxPRI/DRxSEC Hold After ACMx_CLK

1.5

Switching Characteristics

tSCTLCS

ACM Controls (ACMx_A[4:0]) Setup Before Assertion of CS

(SC + 1) × tSCLK1 – 3

tHCTLCS

ACM Control (ACMx_A[4:0]) Hold After De-assertion of CS

HC × tACLK + 0.1

tACLKW

ACM Clock Pulse Width

(tSCLK1/2) × (CLKDIV + 1) – 1.5

tACLK

ACM Clock Period

[tSCLK1 × (CKDIV + 1)] or [16]

tHCSACLK

CS Hold to ACMx_CLK Edge

–0.1

tSCSACLK

CS Setup to ACMx_CLK Edge

tACLK – 3.5

1 Whichever is greater.

Figure 48. ACM Timing

CSPOL = 1/0

tSCSACLK

ACM

CONTROLS

DRxPRI/

DRxSEC

tACLK

SCTLCS

tSDR

tHDR

ACM_CLK

CLKPOL = 1/0

tHCSACLK

HCTLCS

ADSP-BF607 Datasheet(PDF) 93 Page - Analog Devices

ADSP-BF607 Datasheet(HTML) 93 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL