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ADSP-BF607 Datasheet(PDF) 78 Page - Analog Devices |
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ADSP-BF607 Datasheet(HTML) 78 Page - Analog Devices |
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78 / 112 page  Rev. 0 | Page 78 of 112 | June 2013 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 47. Serial Ports—Internal Clock VDD_EXT 1.8V Nominal VDD_EXT 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements tSFSI Frame Sync Setup Before SPT_CLK (Externally Generated Frame Sync in either Transmit or Receive Mode)1 16.8 12 ns tHFSI Frame Sync Hold After SPT_CLK (Externally Generated Frame Sync in either Transmit or Receive Mode) 1 0–0.5 ns tSDRI Receive Data Setup Before SPT_CLK 1 4.8 3.4 ns tHDRI Receive Data Hold After SPT_CLK1 1.5 1.5 ns Switching Characteristics tDFSI Frame Sync Delay After SPT_CLK (Internally Generated Frame Sync in Transmit or Receive Mode) 2 3.5 3.5 ns tHOFSI Frame Sync Hold After SPT_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)2 –1.0 –1.0 ns tDDTI Transmit Data Delay After SPT_CLK2 3.5 3.5 ns tHDTI Transmit Data Hold After SPT_CLK 2 –1.25 –1.25 ns tSCLKIW SPT_CLK Width for Internal SPT_CLK Data/FS Transmit3 [0.5 × tSCLK1 – 1.5] or [4.5] [0.5 × tSCLK1 – 1.5] or [4.5] ns SPT_CLK Width for Internal SPT_CLK Data/FS Receive [0.5 × tSCLK1 – 1.5] or [6.5] [0.5 × tSCLK1 – 1.5] or [6.5] ns tSPTCLK SPT_CLK Period for Internal SPT_CLK Data/FS Transmit 3 [tSCLK1 – 1.5] or [12] [tSCLK1 – 1.5] or [12] ns tSPTCLK SPT_CLK Period for Internal SPT_CLK Data/FS Receive 3 [tSCLK1 – 1.5] or [16] [tSCLK1 – 1.5] or [16] ns 1 Referenced to the sample edge. 2 Referenced to drive edge. 3 Whichever is greater. |
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