ADSP-BF607 datasheet(70/112 Pages) AD

70 / 112 page

Rev. 0

Page 70 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

Mobile DDR SDRAM Clock and Control Cycle Timing

Mobile DDR SDRAM Read Cycle Timing

Table 39. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V

200 MHz

Parameter

Min

Max

Unit

Switching Characteristics

tCK

Clock Cycle Time (CL = 2 Not Supported)

tCH

Minimum Clock Pulse Width

0.45

0.55

tCK

tCL

Maximum Clock Pulse Width

0.45

0.55

tCK

tIS

Control/Address Setup Relative to DMC0_CK Rise

tIH

Control/Address Hold Relative to DMC0_CK Rise

Figure 22. Mobile DDR SDRAM Clock and Control Cycle Timing

Table 40. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V

200 MHz

Parameter

Min

Max

Unit

Timing Requirements

tQH

DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS

1.75

tDQSQ

DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated

DMC0_DQ Signals

0.4

tRPRE

Read Preamble

0.9

1.1

tCK

tRPST

Read Postamble

0.4

0.6

tCK

Figure 23. Mobile DDR SDRAM Controller Input AC Timing

NOTE: CONTROL =

DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.

ADDRESS = DMC0_A00-13, AND DMC0_BA0-1.

DMC0_CK

ADDRESS

CONTROL

tIS

tIH

tCK

tCH

tCL

DMC0_CK

DMC0_DQS

tDQSQ

DMC0_DQS

(DATA)

Dn+1

Dn+2

Dn+3

tRPRE

tRPST

tQH

ADSP-BF607 Datasheet(PDF) 70 Page - Analog Devices

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