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ADSP-BF607 Datasheet(PDF) 72 Page - Analog Devices |
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ADSP-BF607 Datasheet(HTML) 72 Page - Analog Devices |
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72 / 112 page  Rev. 0 | Page 72 of 112 | June 2013 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Enhanced Parallel Peripheral Interface Timing Table 42 and Figure 25 on Page 72, Figure 27 on Page 74, Figure 26 on Page 73, and Figure 28 on Page 74 describe enhanced parallel peripheral interface timing operations. Table 42. Enhanced Parallel Peripheral Interface—Internal Clock VDD_EXT 1.8V Nominal VDD_EXT 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements tSFSPI External Frame Sync Setup Before EPPI_ CLK 7.9 6.5 ns tHFSPI External Frame Sync Hold After EPPI_CLK 0 0 ns tSDRPI Receive Data Setup Before EPPI_CLK 7.9 6.5 ns tHDRPI Receive Data Hold After EPPI_CLK 0 0 ns Switching Characteristics tPCLKW EPPI_CLK Width for Data Transmit, FS External Data/FS Transmit1 [0.5 × tSCLK0 – 1.5] or [4.5] [0.5 × tSCLK0 – 1.5] or [4.5] ns EPPI_CLK Width for Data Transmit, FS Internal Data/FS Receive1 [0.5 × tSCLK0 – 1.5] or [6.5] [0.5 × tSCLK0 – 1.5] or [6.5] ns tPCLK EPPI_CLK Period for Data Receive, FS External Data/FS Transmit1 [tSCLK0 – 1.5] or [12] [tSCLK0 – 1.5] or [12] ns EPPI_CLK Period for Data Receive, FS Internal Data/FS Receive 1 [tSCLK0 – 1.5] or [16] [tSCLK0 – 1.5] or [16] ns tDFSPI Internal Frame Sync Delay After EPPI_CLK 3.5 3.5 ns tHOFSPI Internal Frame Sync Hold After EPPI_CLK –0.5 –0.5 ns tDDTPI Transmit Data Delay After EPPI_CLK 3.5 3.5 ns tHDTPI Transmit Data Hold After EPPI_CLK –0.5 –0.5 ns tSFS3GE External FS3 Input Setup Before EPPI_CLK Fall Edge in Clock Gating Mode 15.4 14 ns 1 Whichever is greater. Figure 25. PPI GP Receive Mode with Internal Frame Sync Timing tHDRPI tSDRPI tHOFSPI FRAME SYNC DRIVEN DATA SAMPLED tDFSPI tPCLK tPCLKW EPPI_D00-23 EPPI_CLK EPPI_FS1/2 |
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