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ADSP-BF607 Datasheet(PDF) 68 Page - Analog Devices

Part # ADSP-BF607
Description  Blackfin Dual Core Embedded Processor
PDF  112 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF607 Datasheet(HTML) 68 Page - Analog Devices

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Rev. 0
|
Page 68 of 112
|
June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DDR2 SDRAM Read Cycle Timing
Table 37. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V
250 MHz
1
1 In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.
Parameter
Min
Max
Unit
Timing Requirements
tDV
Data Valid Window
1
ns
tDQSQ
DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated DMC0_
DQ Signals
0.35
ns
tQH
DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS
1.6
ns
tRPRE
Read Preamble
0.9
tCK
tRPST
Read Postamble
0.4
tCK
Figure 20. DDR2 SDRAM Controller Input AC Timing
DDR2_CLKx
DDR2_DQSn
tAC
tRPRE
tDQSQ
tDQSQ
tQH
tRPST
DDR2_DATA
DDR2_CLKx
DDR2_DQSn
tDQSCK
tCK
tCH
tCL
tAS
tAH
DDR2_ADDR
DDR2_CTL
tQH



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