ADSP-BF607 datasheet(20/112 Pages) AD

20 / 112 page

Rev. 0

Page 20 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

ETH_CRS

Input

Carrier Sense/RMII Receive Data Valid Multiplexed on alternate clock cycles.

CRS: Asserted by the PHY when either the transmit or receive medium is not idle. De-asserted when both

are idle.

RXDV: Asserted by the PHY when the data on RXDn is valid.

ETH_MDC

Output

Management Channel Clock Clocks the MDC input of the PHY.

ETH_MDIO

I/O

Management Channel Serial Data Bidirectional data bus for PHY control.

ETH_PTPAUXIN

Input

PTP Auxiliary Trigger Input Assert this signal to take an auxiliary snapshot of the time and store it in

the auxiliary time stamp FIFO.

ETH_PTPCLKIN

Input

PTP Clock Input Optional external PTP clock input.

ETH_PTPPPS

Output

PTP Pulse-Per-Second Output When the Advanced Time Stamp feature is enabled, this signal is

asserted based on the PPS mode selected. Otherwise, PTPPPS is asserted every time the seconds counter

is incremented.

ETH_REFCLK

Input

Reference Clock Externally supplied Ethernet clock.

ETH_RXDn

Input

Receive Data n Receive data bus.

ETH_TXDn

Output

Transmit Data n Transmit data bus.

ETH_TXEN

I/O

Transmit Enable When asserted indicates that the data on TXDn is valid.

JTG_EMU

Output

Emulation Output JTAG emulation flag.

JTG_TCK

Input

Clock JTAG test access port clock.

JTG_TDI

Input

Serial Data In JTAG test access port data input.

JTG_TDO

Output

Serial Data Out JTAG test access port data output.

JTG_TMS

Input

Mode Select JTAG test access port mode select.

JTG_TRST

Input

Reset JTAG test access port reset.

LP_ACK

I/O

Acknowledge Provides handshaking. When the link port is configured as a receiver, ACK is an output.

When the link port is configured as a transmitter, ACK is an input.

LP_CLK

I/O

Clock When the link port is configured as a receiver, CLK is an input. When the link port is configured as

a transmitter, CLK is an output.

LP_Dn

I/O

Data n Data bus. Input when receiving, output when transmitting.

PPI_CLK

I/O

Clock Input in external clock mode, output in internal clock mode.

PPI_Dnn

I/O

Data n Bidirectional data bus.

PPI_FS1

I/O

Frame Sync 1 (HSYNC) Behavior depends on PPI mode. See the PPI chapter in the processor hardware

reference for more details.

PPI_FS2

I/O

Frame Sync 2 (VSYNC) Behavior depends on PPI mode. See the PPI chapter in the processor hardware

reference for more details.

PPI_FS3

I/O

Frame Sync 3 (FIELD) Behavior depends on PPI mode. See the PPI chapter in the processor hardware

reference for more details.

PWM_AH

Output

Channel A High Side High side drive signal.

PWM_AL

Output

Channel A Low Side Low side drive signal.

PWM_BH

Output

Channel B High Side High side drive signal.

PWM_BL

Output

Channel B Low Side Low side drive signal.

PWM_CH

Output

Channel C High Side High side drive signal.

PWM_CL

Output

Channel C Low Side Low side drive signal.

PWM_DH

Output

Channel D High Side High side drive signal.

PWM_DL

Output

Channel D Low Side Low side drive signal.

PWM_SYNC

Input

PWM External Sync This input is for an externally generated sync signal. If the sync signal is internally

generated no connection is necessary.

PWM_TRIPn

Input

Shutdown Input n When asserted the selected PWM channel outputs are shut down immediately.

Px_nn

I/O

Position n General purpose input/output. See the GP Ports chapter in the processor hardware reference

for programming information.

Table 6. Detailed Signal Descriptions (Continued)

Signal Name

Direction

Description

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