ADSP-BF607 datasheet(67/112 Pages) AD

67 / 112 page

Rev. 0

Page 67 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

Bus Request/Bus Grant

DDR2 SDRAM Clock and Control Cycle Timing

Table 35. Bus Request/Bus Grant

VDD_EXT

1.8V/3.3V Nominal

Parameter

Min

Max

Unit

Switching Characteristics

tDBGBR

SMC0_BG Delay After SMC0_BR

2.5 × tSCLK0

3.5 × tSCLK0 + 17.5

tENGDAT

DATA Enable After SMC0_BG Deassertion

–3

tDBGDAT

DATA Disable After SMC0_BG Assertion

Figure 18. Bus Request/Bus Grant

SMC0_BR

SMC0_BG

tDBGBR

SMC0 DATA/ADDRESS

CONTROL

tENGDAT

tDNGDAT

Table 36. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V

250 MHz

Parameter

Min

Max

Unit

Switching Characteristics

tCK

Clock Cycle Time (CL = 2 Not Supported)

tCH

Minimum Clock Pulse Width

0.45

0.55

tCK

tCL

Maximum Clock Pulse Width

0.45

0.55

tCK

tIS

Control/Address Setup Relative to DMC0_CK Rise

350

tIH

Control/Address Hold Relative to DMC0_CK Rise

475

Figure 19. DDR2 SDRAM Clock and Control Cycle Timing

NOTE: CONTROL =

DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.

ADDRESS = DMC0_A00-13, AND DMC0_BA0-1.

DMC0_CK

ADDRESS

CONTROL

tIS

tIH

tCK

tCH

tCL

DMC0_CK

ADSP-BF607 Datasheet(PDF) 67 Page - Analog Devices

ADSP-BF607 Datasheet(HTML) 67 Page - Analog Devices

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