ADSP-BF607 datasheet(59/112 Pages) AD

59 / 112 page

Rev. 0

Page 59 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

TIMING SPECIFICATIONS

Specifications are subject to change without notice.

Clock and Reset Timing

Table 26 and Figure 10 describe clock and reset operations. Per

the CCLK, SYSCLK, SCLK0, SCLK1, DCLK, and OCLK timing

specifications in Table 17 on Page 53, combinations of 

SYS_CLKIN and clock multipliers must not select clock rates in

excess of the processor’s maximum instruction rate.

Table 26. Clock and Reset Timing

VDD_EXT

1.8 V/3.3V Nominal

Parameter

Min

Max

Unit

Timing Requirements

fCKIN

SYS_CLKIN Frequency (using a crystal)

1, 2, 3

MHz

fCKIN

SYS_CLKIN Frequency (using a crystal oscillator)1, 2, 3

MHz

tCKINL

SYS_CLKIN Low Pulse

6.67

tCKINH

SYS_CLKIN High Pulse1

6.67

tWRST

SYS_HWRST Asserted Pulse Width Low

11 × tCKIN

1 Applies to PLL bypass mode and PLL non bypass mode.

2 The tCKIN period (see Figure 10) equals 1/fCKIN.

3 If the CGU_CTL.DF bit is set, the minimum f

CKIN specification is 40 MHz.

4 Applies after power-up sequence is complete. See Table 27 and Figure 11 for power-up reset timing.

Figure 10. Clock and Reset Timing

SYS_CLKIN

tWRST

tCKIN

tCKINL

tCKINH

SYS_HWRST

ADSP-BF607 Datasheet(PDF) 59 Page - Analog Devices

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