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S25FS256S Datasheet(PDF) 43 Page - SPANSION |
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S25FS256S Datasheet(HTML) 43 Page - SPANSION |
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43 / 154 page  November 6, 2013 S25FS-S_00_04 S25FS-S Family 43 Da ta Shee t (Prelim i nar y ) 6.5.1 DDR Input Timing Figure 6.14 SPI DDR Input Timing 6.5.2 DDR Output Timing Figure 6.15 SPI DDR Output Timing Figure 6.16 SPI DDR Data Valid Window 1. Data Valid calculation at 80 MHz: tDV = tCH(min) – tIORT – tIO_SKEW – tIHTU - ΔtV tDV = 5.62 ns – 1.5 ns – 400 ps – 130 ps – 80 ps tDV = 3.51 ns (56% of the total half clock in the worst case scenario) CS# SCK SI_or_IO SO MSB IN LSB IN tCSS tCSS tCSH tCSH tCS tSU tSU tHD tHD CS# SCK SI SO_or_IO MSB LSB tCS tHO tV tV tDIS SCK IO0 IO1 IO2 IO3 IO_valid Slow D1 . Slow D2 Fast D1 Fast D2 D1 D2 tV tV tV tV tIO_SKEW tDV tCL tCL tCH tIORT_or_tIOFT tIHTU tILTU |
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