S25FS256S datasheet(99/154 Pages) SPANSION

99 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

10.3.7

Clear Status Register (CLSR 30h or 82h)

The Clear Status Register command resets bit SR1V[5] (Erase Fail Flag) and bit SR1V[6] (Program Fail

Flag). It is not necessary to set the WEL bit before a Clear Status Register command is executed. The Clear

Status Register command will be accepted even when the device remains busy with WIP set to 1, as the

device does remain busy when either error bit is set. The WEL bit will be unchanged after this command is

executed.

The legacy Clear Status Register (CLSR 30h) instruction may be disabled and the 30h instruction value

instead used for a program / erase resume command - see Configuration Register 3 on page 69. The Clear

Status Register alternate instruction (CLSR 82h) is always available to clear the Status Register.

Figure 10.17 Clear Status Register (CLSR) Command Sequence

This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock

cycles per byte.

Figure 10.18 Clear Status Register (CLSR) Command Sequence QPI Mode

10.3.8

Program NVDLR (PNVDLR 43h)

Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN)

command must be issued and decoded by the device. After the Write Enable (WREN) command has been

decoded successfully, the device will set the Write Enable Latch (WEL) to enable the PNVDLR operation.

The PNVDLR command is entered by shifting the instruction and the data byte on SI.

CS# must be driven to the logic high state after the eighth bit of data has been latched. If not, the PNVDLR

command is not executed. As soon as CS# is driven to the logic high state, the self-timed PNVDLR operation

is initiated. While the PNVDLR operation is in progress, the Status Register may be read to check the value of

the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PNVDLR cycle,

and is a 0. when it is completed. The PNVDLR operation can report a program error in the P_ERR bit of the

Status Register. When the PNVDLR operation is completed, the Write Enable Latch (WEL) is set to a 0. The

maximum clock frequency for the PNVDLR command is 133 MHz.

Figure 10.19 Program NVDLR (PNVDLR) Command Sequence

CS#

SCK

Phase

Instruction

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruction

CS#

SCK

Phase

Instruction

Input Data

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