S25FS256S datasheet(100/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

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(Pre limin ar y)

10.3.9

Write VDLR (WVDLR 4Ah)

Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN)

command must be issued and decoded by the device. After the Write Enable (WREN) command has been

decoded successfully, the device will set the Write Enable Latch (WEL) to enable WVDLR operation.

The WVDLR command is entered by shifting the instruction and the data byte on SI.

CS# must be driven to the logic high state after the eighth bit of data has been latched. If not, the WVDLR

command is not executed. As soon as CS# is driven to the logic high state, the WVDLR operation is initiated

with no delays. The maximum clock frequency for the PNVDLR command is 133 MHz.

Figure 10.20 Write VDLR (WVDLR) Command Sequence

10.3.10

Data Learning Pattern Read (DLPRD 41h)

The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP

continuously by providing multiples of eight clock cycles. The maximum operating clock frequency for the

DLPRD command is 133 MHz.

Figure 10.21 DLP Read (DLPRD) Command Sequence

10.3.11

Enter 4-Byte Address Mode (4BAM B7h)

The enter 4-byte Address Mode (4BAM) command sets the volatile Address Length bit (CR2V[7]) to 1 to

change most 3-byte address commands to require 4 bytes of address. The Read SFDP (RSFDP) command

is the only 3-byte command that is not affected by the Address Length bit. RSFDP is required by the JEDEC

JESD216 standard to always have only 3 bytes of address.

A hardware or software reset is required to exit the 4-byte address mode.

Figure 10.22 Enter 4-Byte Address Mode (4BAM B7h) Command Sequence

CS#

SCK

Phase

Instruction

Input Data

CS#

SCK

Phase

Instruction

Repeat Register Read

CS#

SCK

Phase

Instruction

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