S25FS256S datasheet(59/154 Pages) SPANSION

59 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

8.6

Registers

Registers are small groups of memory cells used to configure how the S25FS-S family memory device

operates or to report the status of device operations. The registers are accessed by specific commands. The

commands (and hexadecimal instruction codes) used for each register are noted in each register description.

In legacy SPI memory devices the individual register bits could be a mixture of volatile, non-volatile, or One-

Time Programmable (OTP) bits within the same register. In some configuration options the type of a register

bit could change e.g. from non-volatile to volatile.

The S25FS-S family uses separate non-volatile or volatile memory cell groups (areas) to implement the

different register bit types. However, the legacy registers and commands continue to appear and behave as

they always have for legacy software compatibility. There is a non-volatile and a volatile version of each

legacy register when that legacy register has volatile bits or when the command to read the legacy register

has zero read latency. When such a register is read the volatile version of the register is delivered. During

Power-On Reset (POR), hardware reset, or software reset, the non-volatile version of a register is copied to

the volatile version to provide the default state of the volatile register. When non-volatile register bits are

written the non-volatile version of the register is erased and programmed with the new bit values and the

volatile version of the register is updated with the new contents of the non-volatile version. When OTP bits are

programmed the non-volatile version of the register is programmed and the appropriate bits are updated in

the volatile version of the register. When volatile register bits are written, only the volatile version of the

The type for each bit is noted in each register description. The default state shown for each bit refers to the

state after Power-On Reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or

OTP, the default state is the value of the bit when the device is shipped from Spansion. Non-Volatile bits have

the same cycling (erase and program) endurance as the main flash array.

Table 8.13 OTP Address Map

Region

Byte Address Range (Hex)

Contents

Initial Delivery State (Hex)

Region 0

000

Least Significant Byte of

Spansion Programmed Random

Number

Spansion Programmed Random

Number

...

00F

Most Significant Byte of

Spansion Programmed Random

Number

010 to 013

Region Locking Bits

Byte 10 [bit 0] locks region 0

from programming when = 0

...

Byte 13 [bit 7] locks region

31from programming when = 0

All Bytes = FF

014 to 01F

Reserved for Future Use (RFU)

All Bytes = FF

Region 1

020 to 03F

Available for User Programming

All Bytes = FF

Region 2

040 to 05F

Available for User Programming

All Bytes = FF

...

Available for User Programming

All Bytes = FF

Region 31

3E0 to 3FF

Available for User Programming

All Bytes = FF

S25FS256S Datasheet(PDF) 59 Page - SPANSION

S25FS256S Datasheet(HTML) 59 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL