S25FS256S datasheet(81/154 Pages) SPANSION

81 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

The Password method clears the PPB Lock bit to 0 during POR, or hardware reset to protect the PPB. A 64-

bit password may be permanently programmed and hidden for the password method. A command can be

used to provide a password for comparison with the hidden password. If the password matches, the PPB

Lock bit is set to 1 to unprotect the PPB. A command can be used to clear the PPB Lock bit to 0. This method

requires use of a password to control PPB protection.

The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP

9.4.1

ASP Register

The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP)

features. See Table 8.27, ASP Register (ASPR) on page 73.

As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors

unprotected, when power is applied. The device programmer or host system must then choose which sector

protection method to use. Programming either of the, one-time programmable, Protection Mode Lock bits,

locks the part permanently in the selected mode:

 ASPR[2:1] = “11” = No ASP mode selected, Persistent Protection mode is the default.

 ASPR[2:1] = “10” = Persistent Protection mode permanently selected.

 ASPR[2:1] = “01” = Password Protection mode permanently selected.

 ASPR[2:1] = “00” is an Illegal condition, attempting to program more than one bit to zero results in a

programming failure.

ASP register programming rules:

 If the password mode is chosen, the password must be programmed prior to setting the Protection Mode

Lock bits.

 Once the Protection mode is selected, the following OTP Configuration Register bits are permanently

protected from programming and no further changes to the OTP register bits is allowed:

– CR1NV[5:2]

– CR2NV

– CR3NV

– CR4NV

– ASPR

– PASS

–NVDLR

– If an attempt to change any of the registers above, after the ASP mode is selected, the operation will

fail and P_ERR (SR1V[6]) will be set to 1.

The programming time of the ASP register is the same as the typical page programming time. The system

can determine the status of the ASP register programming operation by reading the WIP bit in the Status

See Sector Protection States Summary on page 83.

S25FS256S Datasheet(PDF) 81 Page - SPANSION