S25FS256S datasheet(66/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

8.6.4

Configuration Register 2

Configuration Register 2 controls certain interface functions. The register bits can be read and changed using

the Read Any Register and Write Any Register commands. The non-volatile version of the register provides

the ability to set the POR, hardware reset, or software reset state of the controls. These configuration bits are

OTP and may only have their default state changed to the opposite value one time during system

configuration. The volatile version of the register controls the feature behavior during normal operation.

8.6.4.1

Configuration Register 2 Non-Volatile (CR2NV)

Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).

Address Length Non-Volatile CR2NV[7]: This bit controls the POR, hardware reset, or software reset state

of the expected address length for all commands that require address and are not fixed 3-byte only or 4-byte

(32-bit) only address. Most commands that need an address are legacy SPI commands that traditionally used

3-byte (24-bit) address. For device densities greater than 128 Mbit a 4-byte address is required to access the

entire memory array. The address length configuration bit is used to change most 3-byte address commands

to expect 4-byte address. See Table 10.1, S25FS-S Family Command Set (sorted by function) on page 88 for

command address length. The use of 4-byte address length also applies to the 128-Mbit member of the

S25FS-S family so that the same 4-byte address hardware and software interface may be used for all family

members to simplify migration between densities. The 128-Mbit member of the S25FS-S family simply

ignores the content of the fourth, high order, address byte. This non-volatile address length configuration bit

enables the device to start immediately (boot) in 4-byte address mode rather than the legacy 3-byte address

mode.

QPI Non-Volatile CR2NV[6]: This bit controls the POR, hardware reset, or software reset state of the

expected instruction width for all commands. Legacy SPI commands always send the instruction one bit wide

(serial I/O) on the SI (IO0) signal. The S25FS-S family also supports the QPI Mode in which all transfers

between the host system and memory are 4-bits wide on IO0 to IO3, including all instructions. This non-

volatile QPI configuration bit enables the device to start immediately (boot) in QPI Mode rather than the

legacy serial instruction mode. When this bit is programmed to QPI Mode, the QUAD_NV bit is also

programmed to Quad Mode (CR1NV[1]=1). The recommended procedure for moving to QPI Mode is to first

use the WRAR command to set CR2V[6]=1, QPI Mode. The volatile register write for QPI Mode has a short

and well defined time (tCS) to switch the device interface into QPI Mode. Following commands can then be

immediately sent in QPI protocol. The WRAR command can be used to program CR2NV[6]=1, followed by

polling of SR1V[0] to know when the programming operation is completed. Similarly, to exit QPI Mode, the

WRAR command is used to clear CR2V[6]=0. CR2NV[6] cannot be erased to 0 because it is OTP.

IO3 Reset Non-Volatile CR2NV[5]: This bit controls the POR, hardware reset, or software reset state of the

IO3 signal behavior. Most legacy SPI devices do not have a hardware reset input signal due to the limited

signal count and connections available in traditional SPI device packages. The S25FS-S family provides the

option to use the IO3 signal as a hardware reset input when the IO3 signal is not in use for transferring

information between the host system and the memory. This non-volatile IO3 Reset configuration bit enables

the device to start immediately (boot) with IO3 enabled for use as a RESET# signal.

Table 8.19 Configuration Register 2 Non-Volatile (CR2NV)

Bits

Field Name

Function

Type

Default

State

Description

AL_NV

Address Length

OTP

1 = 4-byte address.

0 = 3-byte address.

QA_NV

QPI

1 = Enabled - QPI (4-4-4) protocol in use.

0 = Disabled - Legacy SPI protocols in use, instruction is

always serial on SI.

IO3R_NV

IO3 Reset

1 = Enabled - IO3 is used as RESET# input when CS# is

high or Quad Mode is disabled CR1V[1]=1.

0 = Disabled - IO3 has no alternate function, hardware

reset is disabled.

RFU

Reserved

Reserved For Future Use.

RL_NV

Read Latency

0 to 15 latency (dummy) cycles following read address

or continuous mode bits.

Note that bit 3 has a default value of 1 and may be

programmed one time to 0 but cannot be returned to 1.

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