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S25FS256S Datasheet(PDF) 62 Page - SPANSION

Part # S25FS256S
Description  MirrorBit Flash Non-Volatile Memory
PDF  154 Pages
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S25FS256S Datasheet(HTML) 62 Page - SPANSION

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S25FS-S Family
S25FS-S_00_04 November 6, 2013
Data
Sheet
(Pre limin ar y)
Write Enable Latch (WEL) SR1V[1]: The WEL bit must be set to 1 to enable program, write, or erase
operations as a means to provide protection against inadvertent changes to memory or register values. The
Write Enable (WREN) command execution sets the Write Enable Latch to a 1 to allow any program, erase, or
write commands to execute afterwards. The Write Disable (WRDI) command can be used to set the Write
Enable Latch to a 1 to prevent all program, erase, and write commands from execution. The WEL bit is
cleared to 0 at the end of any successful program, write, or erase operation. Following a failed operation the
WEL bit may remain set and should be cleared with a WRDI command following a CLSR command. After a
power-down / power-up sequence, hardware reset, or software reset, the Write Enable Latch is set to a 0 The
WRR or WRAR command does not affect this bit.
Write-In-Progress (WIP) SR1V[0]: Indicates whether the device is performing a program, write, erase
operation, or any other operation, during which a new operation command will be ignored. When the bit is set
to a 1 the device is busy performing an operation. While WIP is 1, only Read Status (RDSR1 or RDSR2),
Read Any Register (RDAR), Erase Suspend (ERSP), Program Suspend (PGSP), Clear Status Register
(CLSR), and software reset (RESET) commands are accepted. ERSP and PGSP will only be accepted if
memory array erase or program operations are in progress. The Status Register E_ERR and P_ERR bits are
updated while WIP =1. When P_ERR or E_ERR bits are set to 1, the WIP bit will remain set to 1 indicating the
device remains busy and unable to receive new operation commands. A Clear Status Register (CLSR)
command must be received to return the device to standby mode. When the WIP bit is cleared to 0 no
operation is in progress. This is a read-only bit.
8.6.2
Status Register 2 Volatile (SR2V)
Related Commands: Read Status Register 2 (RDSR2 07h), Read Any Register (RDAR 65h).
Status Register 2 does not have user programmable non-volatile bits, all defined bits are volatile read only
status. The default state of these bits are set by hardware.
Erase Status (ESTAT) SR2V[2]: The Erase Status bit indicates whether the sector, selected by an
immediately preceding Erase Status command, completed the last Erase command on that sector. The Erase
Status command must be issued immediately before reading SR2V to get valid Erase Status. Reading SR2V
during a program or erase suspend does not provide valid Erase Status. The Erase Status bit can be used by
system software to detect any sector that failed its last erase operation. This can be used to detect erase
operations failed due to loss of power during the erase operation.
Erase Suspend (ES) SR2V[1]: The Erase Suspend bit is used to determine when the device is in Erase
Suspend mode. This is a status bit that cannot be written by the user. When Erase Suspend bit is set to 1, the
device is in Erase Suspend mode. When Erase Suspend bit is cleared to 0, the device is not in erase
suspend mode. Refer to Section 10.6.5, Program or Erase Suspend (PES 85h, 75h, B0h) on page 120 for
details about the Erase Suspend/Resume commands.
Program Suspend (PS) SR2V[0]: The Program Suspend bit is used to determine when the device is in
Program Suspend mode. This is a status bit that cannot be written by the user. When Program Suspend bit is
set to 1, the device is in Program Suspend mode. When the Program Suspend bit is cleared to 0, the device
is not in Program Suspend mode. Refer to Section 10.6.5, Program or Erase Suspend (PES 85h, 75h, B0h)
on page 120 for details.
Table 8.16 Status Register 2 Volatile (SR2V)
Bits
Field Name
Function
Type
Default State
Description
7
RFU
Reserved
0
Reserved for Future Use.
6
RFU
Reserved
0
Reserved for Future Use.
5
RFU
Reserved
0
Reserved for Future Use.
4
RFU
Reserved
0
Reserved for Future Use.
3
RFU
Reserved
0
Reserved for Future Use.
2
ESTAT
Erase Status
Volatile
Read Only
0
1 = Sector Erase Status command result =
Erase Completed.
0 = Sector Erase Status command result =
Erase Not Completed.
1
ES
Erase Suspend
Volatile
Read Only
0
1 = In Erase Suspend mode.
0 = Not in Erase Suspend mode.
0
PS
Program
Suspend
Volatile
Read Only
0
1 = In Program Suspend mode.
0 = Not in Program Suspend mode.



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