AM8530 datasheet(123/194 Pages) AMD

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AMD

6–13

The transmitter uses the character stored in WR6 as a time fill. The sync character can

be either six or eight bits, depending on the state of the 6-bit/8-bit Sync bit in WR10. If the

Sync Character Load Inhibit bit is set, the receiver strips the contents of WR6 from the

data stream if received within character boundaries.

Bisync (01). The concatenation of WR7 with WR6 is used for receiver synchronization

and as time fill by the transmitter. The sync character can be 12 or 16 bits in the receiver,

depending on the state of the 6-bit/8-bit Sync bit in WR10. The transmitted character is

always 16 bits.

SDLC Mode (10). In this mode, SDLC is selected and requires a flag (01111110) to be

written to WR7. The receiver address field should be written to WR6. The SDLC CRC

polynomial must also be selected (WR5) in SDLC mode.

External Sync Mode (11). In this mode, the SCC expects external logic to signal charac-

ter synchronization via the SYNC pin. If the crystal oscillator option is selected (in

WR11), the internal SYNC signal is forced to ‘0’. Also in this mode, bits D7–D6 of this

SYNC Mode on page 4–41. The transmitter is in Monosync mode using the contents of

WR6 as the time fill with the sync character length specified by the 6-bit/8-bit Sync bit in

WR10.

Bits 3 and 2: Stop Bits 1 and 0

These bits determine the number of stop bits added to each asynchronous character that

is transmitted. The receiver always checks for one stop bit in Asynchronous mode. A

Special mode specifies that a Synchronous mode is to be selected. D2 is always set to

‘1’, by a channel or hardware reset to ensure that the

SYNC pin is in a known state after a

reset.

Synchronous Modes Enable (00). This bit combination selects one of the synchronous

modes specified by bits D4, D5, D6, and D7 of this register and forces the 1X Clock mode

internally.

1 Stop Bit/Character (1). This bit selects Asynchronous mode with one stop bit per char-

acter.

11/2 Stop Bits/Character (10). These bits select Asynchronous mode with 1-1/2 stop bits

per character. This mode cannot be used with the 1X clock mode.

2 Stop Bits/Character (11). These bits select Asynchronous mode with two stop bits per

transmitted character and check for one received stop bit.

Bit 1: Parity Even/Odd

This bit determines whether parity is checked as even or odd. A ‘1’ programmed here

selects even parity, and a ‘0’ selects odd parity. This bit is ignored if the Parity Enable bit

is not set.

Bit 0: Parity Enable

When this bit is set, an additional bit position beyond those specified in the bits/character

control is added to the transmitted data and is expected in the receive data. The Re-

ceived Parity bit is transferred to the CPU as part of the data unless eight bits per charac-

ter is selected in the receiver.

6.2.6

Write Register 5 (Transmit Parameter and Controls)

WR5 contains control bits that affect the operation of the transmitter. D2 affects both the

transmitter and the receiver. Bit positions for WR5 are shown in Figure 6–6. This register

is readable by executing a read to RR5 when D0 of WR15 and D6 of WR7’ are set to ‘1’.

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