AM8530 datasheet(124/194 Pages) AMD

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6–14

D7 D6 D5 D4 D3 D2 D1 D0

Tx CRC Enable

RTS

SDLC/CRC-16

Send Break

Tx 5 Bits (or less)/Character

Tx 7 Bits/Character

Tx 6 Bits/Character

Tx 8 Bits/Character

Tx Enable

DTR

Figure 6–6. Write Register 5

Bit 7: Data Terminal Ready

This is the control bit for the

DTR/REQ pin while the pin is in the DTR mode (selected in

WR14). When set,

DTR is Low; when reset, DTR is High. This bit is ignored when DTR/

REQ is programmed to act as a Request pin. This bit is reset by a channel or hardware

reset.

Bits 6 and 5: TX Bits/Character 1 and 0

These bits control the number of bits in each byte transferred to the transmit buffer. Bits

sent must be right justified with least significant bits first.

The Five Or Less mode allows transmission of one to five bits per character; however, the

CPU should format the data character as shown below in Table 6–3. In the Six or Seven

Bits/Character modes, unused data bits are ignored.

Bit 4: Send Break

When set, this bit forces the TxD output to send continuous ‘0’s beginning with the follow-

ing transmit clock, regardless of any data being transmitted at the time. This bit functions

whether or not the transmitter is enabled. When reset, TxD continues to send the con-

tents of the Transmit Shift register, which might be syncs, data, or all ‘1’s. If this bit is set

while in the X21 mode (Monosync and Loop mode selected) and character synchroniza-

tion is achieved in the receiver, this bit is automatically reset and the transmitter begins

sending syncs or data. This bit can also be reset by a channel or hardware reset.

Table 6–3. Transmit Bits/Character

Character Length

5 or less bits/character

7 bits/character

6 bits/character

8 bits/character

Transmitter

1111000

Sends one data bit

111000

Sends two data bits

11000

Sends three data bits

1000

Sends four data bits

000

Sends five data bits

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