AM8530 datasheet(128/194 Pages) AMD

128 / 194 page

AMD

6–18

Bit 4: DTR/REQ Timing Mode

This bit controls the timing of the

DTR/REQ pin. If this bit is set to ‘1’, the deactivation tim-

ing of the

DTR/REQ pin is made identical to the WAIT/REQ pin.

Bit 3: TxD Forced High in SDLC NRZI Mode

If this bit is set to ‘1’, and the transmitter is disabled while the SCC is programmed in

SDLC mode with NRZI encoding, the

TxD pin will be pulled to a high physical state.

Bit 2: Auto RTS Deactivation

This bit synchronizes the deactivation of

RTS with the closing flag of an SDLC frame. If

this bit is set to ‘1’ and the user deactivates

RTS while the CRC characters are being

transmitted, the SCC assures that the last bit of the flag character is transmitted before

deactivating

RTS.

Bit 1: Auto EOM Reset

This bit removes the requirement of having to reset the Tx Underrun/EOM latch during

the transmission of a frame. If this bit is set to ‘1’, the Tx Underrun/EOM latch will be

automatically reset by the SCC after the first byte is transmitted.

Bit 0: Auto Tx Flag

This bit removes the requirement of having to wait for the mark idle and flag characters to

be sent before the first data character of a new frame is written to the transmit buffer reg-

ister (WR8). If this bit is set to ‘1’, the user need only write the first character to the trans-

mit buffer. The SCC will then transmit the opening flag followed by data.

6.2.9

Write Register 8 (Transmit Buffer)

WR8 is the transmit buffer register.

6.2.10

Write Register 9 (Master Interrupt Control)

WR9 is the Master Interrupt Control register and contains the Reset command bits. Only

one WR9 exists in the SCC and can be accessed from either channel. The interrupt con-

trol bits can be programmed at the same time as the Reset command because these bits

are reset only by a hardware reset. Bit positions for WR9 are shown in Figure 6–10.

D7 D6 D5 D4 D3 D2 D1 D0

No Reset

Channel Reset B

Channel Reset A

Force Hardware Reset

VIS

DLC

MIE

STATUS HIGH/

STATUS LOW

Interrupt Masking without

INTACK

Figure 6–10. Write Register 9

AM8530 Datasheet(PDF) 128 Page - Advanced Micro Devices

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