AM8530 datasheet(131/194 Pages) AMD

131 / 194 page

AMD

6–21

001

Transmit Clock

Data

NRZ

NRZI

FM1

FM0

Receive Clock

NRZ

001

Data

NRZI

FM1

FM0

Bit Cell

Figure 6–12. NRZ (NRZI) FM1 (FM0) Timing

Bit 7: CRC Presets ‘1’ or ‘0’

This bit specifies the initialized condition of the receive CRC checker and the transmit

CRC generator. If this bit is set to ‘1’, the CRC generator and checker are preset to ‘1’. If

this bit is set to ‘0’, the CRC generator and checker are preset to ‘0’. Either option can be

selected with either CRC polynomial. In SDLC mode, the transmitted CRC is inverted be-

fore transmission and the received CRC is checked against the bit pattern

“0001110100001111.” This bit is reset by a channel or hardware reset. This bit is ignored

in Asynchronous mode.

Bits 6 and 5: Data Encoding 1 and 2

These bits control the coding method used for both the transmitter and the receiver, as

illustrated in Table 6–5. All of the clocking options are available for all coding methods.

The DPLL in the SCC is useful for recovering clocking information in NRZI and FM

modes. Any coding method can be used in the X1 mode. A hardware reset forces NRZ

mode. Timing for the various modes is shown in Figure 6–12.

AM8530 Datasheet(PDF) 131 Page - Advanced Micro Devices