AM8530 datasheet(130/194 Pages) AMD

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AMD

6–20

Bit 2: Disable Lower Chain

The Disable Lower Chain can be used by the CPU to control the interrupt daisy chain.

Setting this bit to ‘1’ forces the IEO pin Low, preventing lower-priority devices on the daisy

chain from requesting interrupts. This bit is reset by a hardware reset.

Bit 1: No Vector

The No Vector bit controls whether or not the SCC will respond to an interrupt acknowl-

edge cycle by placing a vector on the data bus if the SCC is the highest-priority device

requesting an interrupt. If this bit is set, no vector is returned; i.e., D0–D7 remain three-

stated during an interrupt acknowledge cycle, even if the SCC is the highest-priority de-

vice requesting an interrupt.

Bit 0: Vector Includes Status

The Vector Includes Status bit controls whether or not the Z-SCC will include status infor-

mation in the vector it places on the bus in response to an interrupt acknowledge cycle. If

this bit is set, the vector returned is variable, with the variable field depending on the high-

est-priority IP that is set. Table 6–4 shows the encoding of the status information. This bit

is ignored if the No Vector (NV) bit is set and does not apply if RR2 is read from Chan-

nel B.

6.2.11

Write Register 10 (Miscellaneous Transmitter/

Receiver Control Bits)

WR10 contains miscellaneous control bits for both the receiver and the transmitter. Bit

positions for WR10 are shown in Figure 6–11. This register is readable by executing a

read to RR11 when D0 of WR15 and D6 of WR7’ are set to ‘1’.

D7 D6 D5 D4 D3 D2 D1 D0

6 Bit/8Bit SYNC

Loop Mode

Abort/Flag on Underrun

Go Active on Poll

NRZ

NRZI

FM1 (Transition = 1)

FM0 (Transition = 0)

Mark/Flag Idle

CRC Preset ‘1’ or ‘0”

Figure 6–11. Write Register 10

AM8530 Datasheet(PDF) 130 Page - Advanced Micro Devices