AM8530 datasheet(160/194 Pages) AMD

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SCC Application Notes

AMD

7–11

7.3

INTERRUPT WITHOUT INTACK ASYNCHRONOUS

MODE

7.3.1

Introduction

This section describes the use of the SCC for interrupt-driven Asynchronous mode. As

with the example in the previous chapter, the SCC is set with 8 bits per character, 2 stop

bits, at 9600 baud rate. An external 2.4576 MHz, crystal oscillator is used for baud-rate

generation. Interrupt acknowledge is not generated because of the extra hardware re-

quired to produce this signal. In this chapter, the SCC is also programmed for local loop-

back so that no external loop between the transmit and the receive data lines is needed

for on-board diagnostics. This feature allows the user to test-program the part without

additional hardware to simulate an actual transmit and receive environment.

7.3.2

SCC Interface

Figure 7–4 shows the SCC to CPU interface required for this application. The 8-bit data

bus and control lines all come from the user’s CPU. The control lines are

RD, WR, A/B,

C and CE. The INT signal goes to an interrupt controller which must produce the inter-

rupt vector to the CPU. The PCLK comes from the system clock, or an external crystal

oscillator, up to the maximum rate of the SCC (e.g., 6 MHz for the Am8530A). The IEI

and the

INTACK pins should be pulled up. The baud-rate generator clock is connected to

the

RTxC pin.

7.3.3

SCC Initialization

The initialization of the SCC for interrupt-driven asynchronous communication is divided

into three parts as shown in Table 7–6. Part one programs the operating modes of the

SCC, part two and three enable them. Care must be taken when writing the code to meet

the SCC’s Cycle and Reset Recovery times. The Cycle Recovery time applies to the pe-

riod between any Read or Write cycles to the SCC, and is 6 PCLK cycles. The Reset Re-

covery time applies to a hardware reset caused either by hardware or software; this

recovery time extends the Cycle Recovery time to 11 PCLK cycles.

Data

Control

System

VCC VCC

XTAL

OSC

2.4576 MHz

OSC

PCLK

RTxC

INTACK

IEI

D0 – D7

SCC

Pin 12 For Channel A

Pin 28 For Channel B

Interrupt

Controller

INT

Figure 7–4. SCC Interface

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