AM8530 datasheet(161/194 Pages) AMD

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SCC Application Notes

AMD

7–12

Table 7–6. SCC Initialization Order for Interrupt Driven Asynchronous Mode

Value

Comments

WR9

C0H

Force Hardware Reset

WR4

4CH

x 16 clock, 2 stop bits, no parity

WR2

00H

Interrupt Vector 00

WR3

C0H

Rx 8 bits, Rx disabled

WR5

60H

Tx 8 bits, DTR, RTS, Tx off

WR9

00H

Int Disabled

WR10

00H

NRZ

WR11

56H

Tx & Rx = BRG out, TRxC = BRG out

WR12

06H

Time constant = 6

WR13

00H

Time constant high = 0

WR14

10H

BRG in = RTxC, BRG of, loopback

Enables

WR14

11H

BRG enable

WR3

C1H

Rx enable

WR5

68H

Tx enable

Enable Interrupts

WR1

12H

Rx Int on all char and Tx Int enables

WR9

08H

MIE

7.3.3.1

SCC Operating Modes Programming

WR9 resets SCC to a known state by writing a C0 hex. This command, Force Hardware

Reset, is identical to a hardware reset. It will reset both channels.

WR4 selects asynchronous mode, x16 mode, 2 stop bits and no parity. The x16 mode

means that the clock rate is 16 times the data rate.

WR2 is the interrupt vector of the SCC. Even though a vector is not placed in the bus in

this mode the vector including status is read from RR2. By writing 00H to this register the

status read will be the only bits set in RR2.

WR3 selects 8 bits per character and does not enable the receiver. The 8 bits per charac-

ter allows 8 bits to be assembled from the data stream. The receiver is not enabled at this

time because the SCC is not completely initialized.

WR5 selects 8 bits per character and does not enable the transmitter. The 8 bits per char-

acter allows 8 bits to be sent as data with the least significant bit first. The transmitter is

not enabled at this time because the SCC is not completely initialized.

WR9 selects that there are no interrupts enabled. This will inhibit the SCC from request-

ing an interrupt from the CPU.

WR10 selects NRZ encoding. This selects NRZ coding that is to be used on the transmit-

ter and the receiver.

WR11 selects the

RTxC pin to TTL clock, the transmit and receive clocks source as the

baud-rate generator and the

TRxC pin as a baud-rate generator output.

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