AM8530 datasheet(164/194 Pages) AMD

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SCC Application Notes

AMD

7–15

7.4

INTERFACING TO THE 8086/80186

7.4.1

8086 (Also Called iAPX 86) Overview

The 8086 is a general purpose 16-bit microprocessor CPU. The CPU has a 16 bit data

bus multiplexed with sixteen address outputs. There are four additional address lines

(segment addresses which are multiplexed with STATUS) that increase the memory

range to 1 Mbyte. The 8086 addresses are specified as bytes. In a 16 bit word, the least

significant byte has the higher address. This is compatible with 8080, 8085, Z80 and

PDP11 addressing schemes but differs from the Z8000 and 68000 addressing.

The data bus is “asynchronous;” i.e, the CPU machine cycle can be stretched without

clock manipulation by inserting Wait states between T2 and T3 of a read or write cycle to

accommodate slower memory or peripherals. Unlike the 68000, the 8086 has separate

address spaces for I/O (64 kBytes).

The 8086 can operate in MIN. or MAX. mode. Maximum mode offloads certain bus con-

trol functions to a peripheral device and allows the CPU to operate efficiently in a co-proc-

essor environment. A brief discussion on both the MIN. and the MAX. modes follows.

MIN. mode:

I/O addressing is define by a High or the IO/M output, and activated by

the RD output for reading from memory, or I/O or activated by the WR

output for writing to memory or I/O.

DMA:

The Bus is requested by activating the HOLD input to the 8086. Bus

Grant is confirmed by the HLDA output from the 8086.

MAX. mode:

I/O operation is controlled by two outputs from the 8288.

(8086 plus

IORC: active during Read from I/O

8288)

IOWC: active during Write to I/O

MRDC: active during Read from memory

MWTC: active during Write to memory

DMA:

The Bus is requested and Bus Grant is acknowledged on the same pin

(

RQ/GT0 OR RQ/GT1) through a pulsed handshake.

Interrupts In MIN. and MAX. Modes:

Interrupt is requested by activating the INTR or NMI inputs to the 8086.

Interrupt is acknowledged by the

INTA pin on a MIN. mode 8086 or by the INTA pin on

the 8288 in MAX. mode.

Note: There is no

RD or IORC during the interrupt acknowledge sequence.

7.4.1.1

The 8086 and Am8530H Interface

Most common systems demultiplex address and data. The Am8530H is compatible with

these systems.

Interface between the 8086 and the Am8530H peripheral device shows how to take ad-

vantage of its interrupt structure as shown in Figure 7–6.

INTACK is generated by the

8086’s first

INTA pulse. This allows about 800 nsec for the interrupt daisy chain to settle.

The second

INTA pulse is then gated to the RD pin which places the vector on the bus. At

8 MHz, two Wait States must be inserted. This design is the same when interfacing to the

186. It requires no additional Wait States. Diagrams in Figure 7–7 show the connections

for 74LS74 in both 5 MHz and 8 MHz operations of the 8086. Figure 7–8 is an alternate

implementation which can be used in place of the logic in the dotted area in Figure 7–6.

Note that the falling edge of

WR must be delayed to meet data setup time requirements.

A Wait State must be inserted (not shown) to meet pulse width requirements during a

write.

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