AFE5807 datasheet(43/75 Pages) TI1

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I/V

LPF

V/I

CURRENT CLAMP

DC Offset

Correction Loop

From attenuator

To ADC

AFE5807

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SLOS703C – SEPTEMBER 2010 – REVISED MAY 2013

PROGRAMMABLE GAIN AMPLIFIER (PGA)

After the voltage controlled attenuator, a programmable gain amplifier can be configured as 24dB or 30dB with a

constant input referred noise of 1.75nV/rtHz. The PGA structure consists of a differential voltage-to-current

converter with programmable gain, current clamp( bias control) circuits, a transimpedance amplifier with a

programmable low-pass filter, and a DC offset correction circuit. Its simplified block diagram is shown below:

Figure 68. Simplified Block Diagram of PGA

Low input noise is always preferred in a PGA and its noise contribution should not degrade the ADC SNR too

much after the attenuator. At the minimum attenuation (used for small input signals), the LNA noise dominates; at

the maximum attenuation (large input signals), the PGA and ADC noise dominates. Thus 24dB gain of PGA

achieves better SNR as long as the amplified signals can exceed the noise floor of the ADC.

The PGA current clamp circuit can be enabled (register 51) to improve the overload recovery performance of the

AFE. If we measure the standard deviation of the output just after overload, for 0.5V VCNTL, it is about 3.2 LSBs

in normal case, i.e the output is stable in about 1 clock cycle after overload. With the current clamp circuit

disabled, the value approaches 4 LSBs meaning a longer time duration before the output stabilizes; however,

with the current clamp circuit enabled, there will be degradation in HD3 for PGA output levels > -2dBFS. For

example, for a –2dBFS output level, the HD3 degrades by approximately 3dB.the ADC in the AFE has excellent

overload recovery performance to detect small signals right after the overload. In order to maximize the output

dynamic range, the maximum PGA output level can be above 2Vpp even with the clamp circuit enabled; the ADC

in the AFE has excellent overload recovery performance to detect small signals right after the overload.

NOTE

In the low power and medium power modes, PGA_CLAMP is disabled for saving power if

51[7]=0

The AFE5807 integrates an anti-aliasing filter in the form of a programmable butterworth low-pass filter (LPF) in

the transimpedance amplifier . The LPF is designed as a differential, active, 3rd order filter with a typical 18dB

per octave roll-off. Programmable through the serial interface, the –1dB frequency corner can be set to one of

10MHz, 15MHz, 20MHz, and 30MHz. The filter bandwidth is set for all channels simultaneously.

A selectable DC offset correction circuit is implemented in the PGA as well. This correction circuit is similar to the

one used in the LNA. It extracts the DC component of the PGA outputs and feeds back to the PGA’s

complimentary inputs for DC offset correction. This DC offset correction circuit also has a high-pass response

with a cut-off frequency of 80KHz.

ANALOG TO DIGITAL CONVERTER

The analog-to-digital converter (ADC) of the AFE5807 employs a pipelined converter architecture that consists of

a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction

logic, ensuring excellent differential linearity and no missing codes at the 14-bit level. The 14 bits given out by

each channel are serialized and sent out on a single pair of pins in LVDS format. All eight channels of the

AFE5807 operate from a common input clock (CLKP/M). The sampling clocks for each of the eight channels are

generated from the input clock using a carefully matched clock buffer tree. The 14x clock required for the

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