AFE5807 datasheet(11/75 Pages) TI1

11 / 75 page

AFE5807

www.ti.com

SLOS703C – SEPTEMBER 2010 – REVISED MAY 2013

DIGITAL CHARACTERISTICS

Typical values are at +25°C, AVDD = 3.3V, AVDD_5 = 5V and AVDD_ADC = 1.8V, DVDD = 1.8V, 12bit / 80MSPS unless

otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = 0°C to TMAX = +85°C.

PARAMETER

CONDITION

MIN

TYP

MAX

UNITS(1)

DIGITAL INPUTS/OUTPUTS

VIH

Logic high input voltage

3.3

VIL

Logic low input voltage

0.3

Logic high input current

200

µA

Logic low input current

200

µA

Input capacitance

VOH

Logic high output voltage

SDOUT pin

DVDD

VOL

Logic low output voltage

SDOUT pin

LVDS OUTPUTS

with 100

Ω external differential

Output differential voltage

400

termination

Output offset voltage

Common-mode voltage

1100

FCLKP and FCLKM

1X clock rate

MHz

DCLKP and DCLKM

7X clock rate (65MSPS)

455

MHz

6X clock rate (80MSPS)

480

MHz

tsu

Data setup time(2)

350

Data hold time(2)

350

ADC INPUT CLOCK

CLOCK frequency

MSPS

Clock duty cycle

45%

50%

55%

Sine-wave, ac-coupled

0.5

Vpp

Clock input amplitude,

LVPECL, ac-coupled(3)

1.6

Vpp

differential(VCLKP_ADC–VCLKM_ADC)

LVDS, ac-coupled(3)

0.7

Vpp

Common-mode voltage

biased internally

Clock input amplitude VCLKP_ADC (single-

CMOS CLOCK

1.8

Vpp

ended)

(1)

The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1

with 100

Ω external termination.

(2)

Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear

as reduced timing margins

(3)

According to design and characterization, LVDS and LVPECL CLK input amplitude can be as low as 0.2Vpp

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