AFE5807 datasheet(68/75 Pages) TI1

68 / 75 page

500 Ω

I/VSum

Amp

Cext

Rint/Rext

CW_OUTM

CW_OUTP

LNA

INP

INM

ACT

INPUT

CW_AMPINM

CW_AMPINP

Mixer

Clock

PGA_P

PGA_M

Cext

5 K

500 Ω

S0504-01

AFE5807

SLOS703C – SEPTEMBER 2010 – REVISED MAY 2013

www.ti.com

Figure 92. AFE5807 PGA Test Mode

POWER SUPPLY, GROUNDING AND BYPASSING

In a mixed-signal system design, power supply and grounding design plays a significant role. The AFE5807

distinguishes between two different grounds: AVSS(Analog Ground) and DVSS(digital ground). In most cases, it

should be adequate to lay out the printed circuit board (PCB) to use a single ground plane for the AFE5807.

Care should be taken that this ground plane is properly partitioned between various sections within the system to

minimize interactions between analog and digital circuitry. Alternatively, the digital (DVDD) supply set consisting

of the DVDD and DVSS pins can be placed on separate power and ground planes. For this configuration, the

AVSS and DVSS grounds should be tied together at the power connector in a star layout. In addition, optical

isolator or digital isolators, such as ISO7240, can separate the analog portion from the digital portion completely.

Consequently they prevent digital noise to contaminate the analog portion. Table 13 lists the related circuit blocks

for each power supply. The AFE5807 register settings are maintained when the AFE5807 is in either partial

power down mode or complete power down mode.

Table 14. Supply vs Circuit Blocks

Power Supply

Ground

Circuit Blocks

LNA, attenuator, PGA with current

clamp circuit and BPF, reference

AVDD (3.3VA)

AVSS

circuits, CW summing amplifier,

CW mixer, VCA SPI

LNA, CW clock circuits, reference

AVDD_5V (5VA)

AVSS

circuits

ADC analog and reference

AVDD_ADC (1.8VA)

AVSS

circuits

DVDD (1.8VD)

DVSS

LVDS and ADC SPI

All bypassing and power supplies for the AFE5807 should be referenced to their corresponding ground planes.

All supply pins should be bypassed with 0.1µF ceramic chip capacitors (size 0603 or smaller). In order to

minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible.

Where double-sided component mounting is allowed, these capacitors are best placed directly under the

package. In addition, larger bipolar decoupling capacitors 2.2µF to 10µF, effective at lower frequencies) may also

be used on the main supply pins. These components can be placed on the PCB in proximity (< 0.5 in or 12.7

mm) to the AFE5807 itself.

The AFE5807 has a number of reference supplies needed to be bypassed, such CM_BYP, VHIGH, and

VREF_IN. These pins should be bypassed with at least 1µF; higher value capacitors can be used for better low-

frequency noise suppression. For best results, choose low-inductance ceramic chip capacitors (size 0402, > 1µF)

and place them as close as possible to the device pins.

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