AFE5807 datasheet(65/75 Pages) TI1

65 / 75 page

FPGA Clock/

Noisy Clock

n × (20 to 65)MHz

TI Jitter Cleaner

LMK048X

CDCE72010

CDCM7005

CDCLVP1208

LMK0030X

LMK01000

20 to 65 MHz

ADC CLK

8 Synchronized

ADC CLKs

CDCE72010 has 10

outputs thus the buffer

may not be needed for

64CH systems

B0437-01

AFE5807

www.ti.com

SLOS703C – SEPTEMBER 2010 – REVISED MAY 2013

Figure 91. ADC Clock Distribution Network

The AFE5807 ADC clock input can be driven by differential clocks (sine wave, LVPECL or LVDS) or singled

clocks (LVCMOS) similar to CW clocks as shown in Figure 89. In the single-end case, it is recommended that the

use of low jitter square signals (LVCMOS levels, 1.8V amplitude). See TI document SLYT075 for further details

on the theory.

The jitter cleaner LMK048X, CDCM7005 or CDCE72010 is suitable to generate the AFE5807’s ADC clock and

ensure the performance for the 12bit ADC with 70dBFS SNR. A clock distribution network is shown in Figure 91.

ADC Reference Circuit

The ADC’s voltage reference can be generated internally or provided externally. When the internal reference

mode is selected, the REFP/M becomes output pins and should be floated. When 3[15] =1 and 1[13]=1, the

device is configured to operate in the external reference mode in which the VREF_IN pin should be driven with a

1.4V reference voltage and REFP/M must be left open. Since the input impedance of the VREF_IN is high, no

special drive capability is required for the 1.4V voltage reference

The digital beam-forming algorithm in an ultrasound system relies on gain matching across all receiver channels.

A typical system would have about 12 octal AFEs on the board. In such a case, it is critical to ensure that the

gain is matched, essentially requiring the reference voltages seen by all the AFEs to be the same. Matching

references within the eight channels of a chip is done by using a single internal reference voltage buffer.

Trimming the reference voltages on each chip during production ensures that the reference voltages are well-

matched across different chips. When the external reference mode is used, a solid reference plane on a printed

circuit board can ensure minimal voltage variation across devices. More information on voltage reference design

can be found in the document SLYT339. The dominant gain variation in the AFE5807 comes from the VCA gain

variation. The gain variation contributed by the ADC reference circuit is much smaller than the VCA gain

variation. Hence, in most systems, using the ADC internal reference mode is sufficient to maintain good gain

matching among multiple AFE5807s. In addition, the internal reference circuit without any external components

achieves satisfactory thermal noise and phase noise performance.

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