AN4650 datasheet(77/102 Pages) STMICROELECTRONICS

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AN4650

First-in first-out (FIFO) buffer

102

8.1.5

FIFO_CTRL5 (0Ah)

The FIFO_CTRL5 register contains the FIFO operating mode bits (FIFO_MODE_[2:0]) and

the FIFO output data rate bits (ODR_FIFO_[3:0]).

FIFO operating modes (Table 63) are described in Section 8.2.

When the internal trigger (accelerometer/gyroscope data-ready) is used, the

ODR_FIFO_[3:0] bits define the maximum data rate at which data are stored in FIFO. Data

can be stored in FIFO at a lower data rate using the FIFO decimation factors.

For more information on how to configure the FIFO trigger and the FIFO ODR see

Section 8.3.

Table 62. FIFO ODR selection setting

Table 60. 4th FIFO data set decimation setting

DEC_DS4_FIFO [2:0]

Configuration

000

4th FIFO data set not in FIFO

001

No decimation

010

Decimation with factor 2

011

Decimation with factor 3

100

Decimation with factor 4

101

Decimation with factor 8

110

Decimation with factor 16

111

Decimation with factor 32

Table 61. FIFO_CTRL5 register

ODR

_FIFO_3

ODR

_FIFO_2

ODR

_FIFO_1

ODR

_FIFO_0

FIFO

_MODE_2

FIFO

_MODE_1

FIFO

_MODE_0

ODR_FIFO [3:0]

Configuration

0000

FIFO disabled

0001

FIFO ODR is set to 10 Hz

0010

FIFO ODR is set to 25 Hz

0011

FIFO ODR is set to 50 Hz

0100

FIFO ODR is set to 100 Hz

0101

FIFO ODR is set to 200 Hz

0110

FIFO ODR is set to 400 Hz

0111

FIFO ODR is set to 800 Hz

1000

FIFO ODR is set to 1600 Hz

1001

FIFO ODR is set to 3300 Hz

1010

FIFO ODR is set to 6600 Hz

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