AN4650 datasheet(36/102 Pages) STMICROELECTRONICS

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Interrupt generation

AN4650

36/102

DocID027415 Rev 1

Interrupt generation

In the LSM6DS3 device the interrupt generation is based on accelerometer data only, so, for

interrupt generation purposes, the accelerometer sensor has to be set in an active operating

mode (not in Power-Down); the gyroscope sensor can be configured in Power-Down mode

since it’s not involved in interrupt generation.

The interrupt generator can be configured to detect:



Free-fall;



Wake-up;



6D/4D orientation detection;



Single-tap and double-tap sensing;



Activity/Inactivity recognition.

In addition, the LSM6DS3 can efficiently run the sensor-related features specified in

Android, saving power and enabling faster reaction time. In particular, it has been designed

to implement in hardware:



Significant motion;



Tilt;



Pedometer functions;



Time stamp.

All these interrupt signals, together with FIFO interrupt signals, can be independently driven

to the INT1 and INT2 interrupt pins or checked by reading the dedicated source register bits.

The H_LACTIVE bit of the CTRL3_C register must be used to select the polarity of the

interrupt pins. If this bit is set to 0 (default value), the interrupt pins are active high and they

change from low to high level when the related interrupt condition is verified. Otherwise, if

the H_LACTIVE bit is set to 1 (active low), the interrupt pins are normally at high level and

they change from high to low when interrupt condition is reached.

The PP_OD bit of CTR3_C allows changing the behavior of the interrupt pins from push-pull

to open drain. If the PP_OD bit is set to 0, the interrupt pins are in push-pull configuration

(low-impedance output for both high and low level). When the PP_OD bit is set to 1, only the

interrupt active state is a low-impedance output.

The LIR bit of TAP_CFG allows applying the latched mode to the interrupt signals. When the

LIR bit is set to 1, once the interrupt pin is asserted, it must be reset by reading the related

interrupt source register. If the LIR bit is set to 0, the interrupt signal is automatically reset

when the interrupt condition is no longer verified or after a certain amount of time.

4.1

Interrupt pin configuration

The device is provided with two pins that can be activated to generate either Data Ready or

interrupt signals. The functionality of these pins is selected through the MD1_CFG and

INT1_CTRL registers for the INT1 pin, and through the MD2_CFG and INT2_CTRL

registers for the INT2 pin.

Hereafter the description of these interrupt control registers; the default value of their bits is

equal to 0, which corresponds to ‘disable’. In order to enable the routing of a specific

interrupt signal on the pin, the related bit has to be set to 1.

AN4650 Datasheet(PDF) 36 Page - STMicroelectronics

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