AN4650 datasheet(83/102 Pages) STMICROELECTRONICS

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AN4650

First-in first-out (FIFO) buffer

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the FTH bit of the FIFO_STATUS2 register is set high when the number of samples in FIFO

will reach or exceed the FTH_[11:0] value on the next FIFO write operation.

It is recommended to read faster than 1*ODR the number of samples stored in the FIFO

equal to at least three times the number of the enabled data set, in order to free FIFO slots

for the new data: this allows avoiding loss of data.

If the read procedure is not fast enough, three different cases can be observed:

FIFO sample set is read faster than 1*ODR: data are correctly retrieved because a free

slot is made available before new data is generated.

FIFO sample set is read synchronous to 1*ODR: data are correctly retrieved because a

free slot is made available before new data is generated but FIFO benefits are not

exploited. This case is equivalent to reading data on the data-ready interrupt and does

not reduce the intervention of the host processor compared to the standard

accelerometer reading.

FIFO sample set is read slower than 1*ODR: in this case some data are lost because

data reading is not fast enough to free slots for new data. The number of correctly

recovered samples is related to the difference between the current ODR and the FIFO

sample set reading rate.

Figure 25 shows an example of the Continuous mode usage. In the example, X-Y-Z data

(green cells indicate the sample number) from just one sensor are stored in the FIFO. In

these conditions, the number of samples stored is 4095. In this example the FIFO samples

are read faster than 1 * ODR and no data is lost.

Figure 25. Continuous mode

AN4650 Datasheet(PDF) 83 Page - STMicroelectronics