AN4650 datasheet(39/102 Pages) STMICROELECTRONICS

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AN4650

Interrupt generation

102

The free-fall interrupt signal can be driven to the two interrupt pins by setting to 1 the

INT1_FF bit of the MD1_CFG register or the INT2_FF bit of the MD2_CFG register; it can

also be checked by reading the FF_IA bit of the WAKE_UP_SRC register.

If latch mode is disabled (LIR bit of TAP_CFG is set to 0), the interrupt signal is

automatically reset when the free-fall condition is no longer verified. If latch mode is enabled

and the free-fall interrupt signal is driven to the interrupt pins, once a free-fall event has

occurred and the interrupt pin is asserted, it must be reset by reading the WAKE_UP_SRC

pins, the latch feature does not take effect.

The register used to configure the threshold parameter is named FREE_FALL; the unsigned

threshold value is related to the value of the FF_THS[2:0] field value as indicated in

Table 28. The values given in this table are valid for each accelerometer full-scale value.

Duration time is measured in N/ODR_XL, where N is the content of the FF_DUR[5:0] field of

the FREE_FALL / WAKE_UP_DUR registers and ODR_XL is the accelerometer data rate.

A basic SW routine for the free-fall event recognition is given below.

The sample code exploits a threshold set to 312 mg for free-fall recognition and the event is

notified by hardware through the INT1 pin. The FF_DUR[5:0] field of FREE_FALL /

WAKE_UP_DUR registers is configured like this to ignore events that are shorter than

6/ODR_XL = 6/412 Hz ~= 15 msec in order to avoid false detections.

Table 28. Free-fall threshold LSB value

FREE_FALL - FF_THS[2:0]

Threshold LSB value [mg]

000

156

001

219

010

250

011

312

100

344

101

406

110

469

111

500

Write 60h into CTRL1_XL

// Turn on the accelerometer

// ODR_XL = 416 Hz, FS_XL = 2g

Write 00h into WAKE_UP_DUR

// Set event duration (FF_DUR5 bit)

Write 33h into FREE_FALL

// Set FF threshold (FF_THS[2:0] = 011b)

// Set six samples event duration (FF_DUR[5:0] = 000110b)

Write 10h into MD1_CFG

// FF interrupt driven to INT1 pin

Write 01h into TAP_CFG

// Latch interrupt

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