AN4650 datasheet(49/102 Pages) STMICROELECTRONICS

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AN4650

Interrupt generation

102

This function can be fully programmed by the user in terms of expected amplitude and

timing of the slope data by means of a dedicated set of registers (Figure 17).

The unsigned threshold value is defined using the WK_THS[5:0] bits of dedicated set of

registers WAKE_UP_THS register; the value of 1 LSB of these 6 bits depends on the

selected accelerometer full scale: 1 LSB = (FS_XL)/(26). The threshold is applied to both

positive and negative slope data.

When a certain number of consecutive X,Y,Z slope data is smaller than the configured

threshold, the ODR_XL [3:0] bits of the CTRL1_XL register are bypassed (Inactivity) and the

accelerometer is internally set to 13 Hz although the content of CTRL1_XL is left untouched.

The duration of the Inactivity status to be recognized is defined by the SLEEP_DUR[3:0] bits

of the WAKE_UP_DUR register: 1 LSB corresponds to 512*ODR_XL time, where ODR_XL

is the accelerometer output data rate.

When the Inactivity status is detected, the interrupt is set high for 1/ODR_XL[s] period then

it is automatically deasserted.

When a certain number of consecutive slope data on one axis become bigger than the

threshold, the CTRL1_XL register settings are immediately restored (Activity). The duration

of the Activity status to be recognized is defined by the WAKE_DUR[1:0] bits of the

WAKE_UP_DUR register: 1 LSB corresponds to 1*ODR_XL time, where ODR_XL is the

accelerometer output data rate.

When the Activity status is detected, the interrupt is set high for 1/ODR_XL[s] period then it

is automatically deasserted.

Once the Activity/Inactivity detection function is enabled, the status can be driven to the two

interrupt pins by setting to 1 the INT1_INACT_STATE bit of the MD1_CFG register or the

INT1_INACT_STATE bit of the MD2_CFG register; it can also be checked by reading the

SLEEP_STATE_IA bit of the WAKE_UP_SRC register.

Figure 17. Activity/Inactivity recognition

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