AM3874 datasheet(150/361 Pages) TI

150 / 361 page

AM3874, AM3871

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

www.ti.com

Table 4-8. Pins Used in EMAC[0] MII/GMII, RGMII, and RMII Boot Modes (continued)

SIGNAL NAMES

PIN NO.

MII/GMII

TYPE

RGMII

TYPE

RMII

TYPE

H23

EMAC[0]_MTXD[3]

DEFAULT

G23

EMAC[0]_MTXD[4]

DEFAULT

F27

EMAC[0]_MTXD[5]

DEFAULT

J22

EMAC[0]_MTXD[6]

DEFAULT

H24

EMAC[0]_MTXD[7]

DEFAULT

J23

EMAC[0]_MTXEN

DEFAULT

H28

MDCLK

P24

MDIO

I/O

MDIO

I/O

MDIO

I/O

4.2.7

PCIe Bootmode (PCIE_32 and PCIE_64)

Table 4-9 lists the device pins that are configured by the ROM for the PCIe boot mode.

Table 4-9. Pins Used in PCIe Bootmode

SIGNAL NAME

PIN NO.

TYPE

PCIE_TXP0

AD2

PCIE_TXN0

AD1

PCIE_RXP0

AC2

PCIE_RXN0

AC1

SERDES_CLKIP

AF1

SERDES_CLKN

AF2

4.2.8

UART Bootmode

Table 4-10 lists the device pins that are configured by the ROM for the UART boot mode.

Table 4-10. Pins Used in UART Bootmode

SIGNAL NAME

PIN NO.

TYPE

UART0_RXD

AH5

UART0_TXD

AG5

4.3

Pin Multiplexing Control

Device level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCNTL1 –

PINCNTL270 registers in the Control Module.

Pin multiplexing selects which one of several peripheral pin functions controls the pin's I/O buffer output

data values. Table 4-11 shows the peripheral pin functions associated with each MUXMODE setting for all

multiplexed pins. The default pin multiplexing control for almost every pin is to select MUXMODE = 0x0, in

which case the pin's I/O buffer is 3-stated.

In most cases, the input from each pin is routed to all of the peripherals that share the pin, regardless of

the MUXMODE setting. However, in some cases a constant "0" or "1" value is routed to the associated

peripheral when its peripheral function is not selected to control any output pin. For more details on the

De-Selected Input State (DSIS), see the "MUXED" columns of each Terminal Functions table (Section 3.2,

Terminal Functions).

150

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