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AM3874 Datasheet(PDF) 152 Page - Texas Instruments

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Part # AM3874
Description  AM387x Sitara??ARM Processors
PDF  361 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3874 Datasheet(HTML) 152 Page - Texas Instruments

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AM3874, AM3871
SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013
www.ti.com
Table 4-12. PINCNTLx Register Reset Value Examples
HEX
PINCNTLx
Bits 31:24
Bits 23:20
Bit 19
Bit 18
Bit 17
Bit 16
Bits 15:8
Bits 7:0
REGISTER
ADDRESS
REGISTER
RESET
RESERVED
RESERVED
RSV
RSV
PLLTYPESEL
PLLUDEN
RESERVED
MUXMODE[7:0]
RANGE
NAME
VALUE
0x4814 0800
PINCNTL1
00h
0h
0
1
1
0
00h
00h
0x0006 0000
0x4814 0804
PINCNTL2
00h
0h
1
1
1
0
00h
00h
0x000E 0000
0x4814 0808
PINCNTL3
00h
0h
1
1
1
0
00h
00h
0x000E 0000
…
0x4814 0C34
PINCNTL270
00h
0h
1
1
0
0
00h
00h
0x000C 0000
(1) "(M0)" represents multimuxed option "0" for this pin function, "(M1)" represents multimuxed option "1" for this pin function, ... etc.
(2) Within this MUXMODE setting, EMAC[x] GMII or RGMII pin functions are selected via the RGMII0_EN and/or RGMII1_EN bits (8 and 9, respectively) in the GMII_SEL register
[0x4814_0650] of the Control Module. "0" = GMII (default) and "1" = RGMII.
Table 4-13. PINCNTLx Registers MUXMODE Functions
HEX
REGISTER
MUXMODE[7:0] SETTINGS
REGISTER
PIN
ADDRESS
RESET
NAME
NO.
0x1
0x2
0x4
0x8
0x10
0x20
0x40
0x80
VALUE
0x4814 0800
PINCNTL1
P3
0x0006 0000
SD1_CLK
0x4814 0804
PINCNTL2
P2
0x000E 0000
GP0[0]
SD1_CMD
(M0)
0x4814 0808
PINCNTL3
P1
0x000E 0000
SD1_DAT[0]
0x4814 080C
PINCNTL4
P5
0x000E 0000
SD1_DAT[1]_SDIRQ
0x4814 0810
PINCNTL5
P4
0x000E 0000
SD1_DAT[2]_SDRW
0x4814 0814
PINCNTL6
P6
0x000E 0000
SD1_DAT[3]
0x4814 0818
PINCNTL7
W6
0x000E 0000
DEVOSC_WAKE
SPI[1]_SCS[1]
TIM5_IO
(M1)
GP1[7]
(M0)
0x4814 081C
PINCNTL8
Y6
0x0006 0000
SD0_CLK
GP0[1]
0x4814 0820
PINCNTL9
N1
0x000E 0000
SD0_CMD
GP0[2]
SD1_CMD
(M1)
0x4814 0824
PINCNTL10
R7
0x000E 0000
SD0_DAT[0]
SD1_DAT[4]
GP0[3]
0x4814 0828
PINCNTL11
Y5
0x000E 0000
SD0_DAT[1]_SDIRQ
SD1_DAT[5]
GP0[4]
0x4814 082C
PINCNTL12
Y3
0x000E 0000
SD0_DAT[2]_SDRW
SD1_DAT[6]
GP0[5]
0x4814 0830
PINCNTL13
Y4
0x000E 0000
SD0_DAT[3]
SD1_DAT[7]
GP0[6]
0x4814 0834
PINCNTL14
L5
0x000C 0000
AUD_CLKIN0
MCA[0]_AHCLKX
MCA[3]_AHCLKX
USB1_DRVVBU
MCA[0]_AXR[7]
(M1)
S
0x4814 0838
PINCNTL15
R5
0x000C 0000
AUD_CLKIN1
MCA[1]_AHCLKX
MCA[4]_AHCLKX
GP0[8]
MCA[0]_AXR[8]
(M1)
EDMA_EVT3
(M1)
TIM2_IO
(M1)
0x4814 083C
PINCNTL16
H1
0x000C 0000
AUD_CLKIN2
MCA[2]_AHCLKX
MCA[5]_AHCLKX
GP0[9]
MCA[0]_AXR[9]
(M1)
EDMA_EVT2
(M1)
TIM3_IO
(M1)
0x4814 0840
PINCNTL17
R4
0x0004 0000
MCA[0]_ACLKX
0x4814 0844
PINCNTL18
L3
0x000C 0000
MCA[0]_AFSX
0x4814 0848
PINCNTL19
K2
0x0004 0000
MCA[0]_ACLKR
MCA[5]_AXR[2]
0x4814 084C
PINCNTL20
K1
0x000C 0000
MCA[0]_AFSR
MCA[5]_AXR[3]
152
Device Configurations
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