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AM3874 Datasheet(PDF) 163 Page - Texas Instruments |
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AM3874 Datasheet(HTML) 163 Page - Texas Instruments |
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163 / 361 page  L4S Targets MMU UART 0/1/2/3/4/5 I2C 0/1/2/3 DMTimer 0/1/2/3/4/5/6/7/8 SPI 0/1/2/3 GPIO 0/1/2/3 MCASP 0/1/2 CFG MMCSD 0 /1 ELM RTC WDT 0/1 Mailbox Spinlock HDVPSS HDMIPHY PLLSS Control Module PRCM DCAN 0/1 OCPWP SYNCTIMER32K L4F Targets EMAC SW SATA MCASP 3/4/5 CFG MCASP 3/4/5 DATA L3S Targets MCASP 0/1 / 2 Data MCBSP GPMC HDMI USB L3S Interconnect 100 MHz (Note 1) L3F/L3Mid Interconnect 200 MHz (Note 1) L4S Interconnect 100 MHz (Note1) L4F Interconnect 200 MHz (Note 1) L3F Initiators EDMATC RD 2/3 EDMATC WR 2/3 HDVPSS (2 I/F) ISS SGX530 L3F Initiators EMAC SW SATA DAP L3S Initiators USB2.0 (2 I/F) L3F Targets ISS MMCSD 2 EDMATC 0/1/2/3 EDMACC DEBUGSS DMM DDR0 DDR1 ARM Cortex A8 2 I/F L3F Initiators PCIe MEDIACTL 8 I/F 2 I/F 4 I/F EDMATC RD 0/1 EDMATC WR 0/1 Note 1 : The frequencies specified are for 100% OPP 2 I/F 4 I/F 1 I/F 9 I/F 7 I/F 58 I/F 11 I/F 11 I/F 5 I/F L3F Targets PCIe MEDIACTL SGX530 OCMC SRAM 2 I/F 128b 128b 128b 128b 128b 32b 32b 32b 32b 32b 32b 32b 32b 64b 64b 64b AM3874, AM3871 www.ti.com SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013 5 System Interconnect The device’s various processors, subsystems, and peripherals are interconnected through a switch fabric architecture. The switch fabric is composed of an L3 and L4 interconnect, a switched central resource (SCR), and multiple bridges (for an overview, see Figure 5-1). Not all Initiators in the switch fabric are connected to all Target peripherals. The supported initiator and target connections are designated by a "X" in Table 5-1, Target/Initiator Connectivity. For more detailed information on the device System Interconnect Architecture, see the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7). Figure 5-1. System Interconnect Copyright © 2011–2013, Texas Instruments Incorporated System Interconnect 163 Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
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