AM3874 datasheet(167/361 Pages) TI

167 / 361 page

AM3874, AM3871

www.ti.com

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

Device Operating Conditions

6.1

Absolute Maximum Ratings

(1) (2)

Core (CVDD, CVDD_ARM)

-0.3 V to 1.5 V

I/O, 1.8 V (DVDD_M, DVDD_DDR[0], DVDD_DDR[1], VDDA_1P8, VDDA_ARMPLL_1P8,

-0.3 V to 2.1 V

VDDA_VID0PLL_1P8, VDDA_VID1PLL_1P8, VDDA_AUDIOPLL_1P8,

Supply voltage ranges

VDDA_DDRPLL_1P8, VDDA_L3PLL_1P8, VDDA_PCIE_1P8, VDDA_SATA_1P8,

(Steady State):

VDDA_HDMI_1P8, VDDA_USB0_1P8, VDDA_USB1_1P8, VDDA_VDAC_1P8)

I/O 3.3 V (DVDD, DVDD_GPMC, DVDD_GPMCB, DVDD_SD, DVDD_C)

-0.3 V to 4.0 V

DDR Reference Voltage (VREFSSTL_DDR[0], VREFSSTL_DDR[1])

-0.3 V to 1.1 V

V I/O, 1.5-V pins (Steady State)

-0.3 V to

DVDD_DDR[x] + 0.3

V I/O, 1.8-V pins (Steady State)

-0.3 V to DVDD +

0.3 V

Input and Output voltage

-0.3 V to DVDD_x +

ranges:

0.3 V

V I/O, 3.3-V pins (Steady State)

-0.3 V to DVDD +

0.3 V

-0.3 V to DVDD_x +

0.3 V

Commercial Temperature

0°C to 90°C

Operating junction

Industrial

-40°C to 90°C

temperature range, TJ:

Extended

-40°C to 105°C

Storage temperature

-55°C to 150°C

range, Tstg:

I-test: Silicon Revision 3.0, All I/O pins(3)

±100 mA

Latch-up Performance:

I-test: Silicon Revision 2.1, All I/O pins(3)

±70 mA

Over-Voltage Test, All Supply pins(4)

1.5xVddmax V

ESD-HBM (Human Body Model)(5)

±1000 V

Electrostatic Discharge

(ESD) Performance:

ESD-CDM (Charged-Device Model)(6)

±250 V

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to their associated VSS or VSSA_x.

(3)

Pins stressed per JEDEC JESD78 at 90°C (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times

maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.

(4)

Supplies stressed per JEDEC JESD78 at 90°C (Class II) and passed specified voltage injection.

(5)

Level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe

manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible if necessary precautions

are taken. Pins listed as 1000 V may actually have higher performance.

(6)

Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process, and manufacturing with less than 250-V CDM is possible if necessary precautions

are taken. Pins listed as 250 V may actually have higher performance.

Device Operating Conditions

167

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