AM3874 datasheet(224/361 Pages) TI

224 / 361 page

AM3874, AM3871

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

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Table 8-14. Ethernet MAC Switch Registers (continued)

ARM/L3 MASTERS

EMAC HEX

ACRONYM

ADDRESS RANGE

0x4A10 0040

CPDMA_RX_CH_Map

CPSW CPDMA RX (Port 0 Tx) Switch Priority to DMA Channel Mapping

0x4A10 0050

P1_MAX_BLKS

CPSW Port 1 Maximum FIFO Blocks Register

0x4A10 0054

P1_BLK_CNT

CPSW Port 1 FIFO Block Usage Count (Read Only)

0x4A10 0058

P1_TX_IN_CTL

CPSW Port 1 Transmit FIFO Control

0x4A10 005C

P1_PORT_VLAN

CPSW Port 1 VLAN Register

0x4A10 0060

P1_TX_PRI_MAP

CPSW Port 1 Tx Header Priority to Switch Priority Mapping Register

0x4A10 0064

P1_TS_CTL

CPSW_3GF Port 1 Time Sync Control Register

0x4A10 0068

P1_TS_SEQ_LTYPE

CPSW_3GF Port 1 Time Sync LTYPE (and SEQ_ID_OFFSET)

0x4A10 006C

P1_TS_VLAN

CPSW_3GF Port 1 Time Sync VLAN2 and VLAN2 Register

0x4A10 0070

SL1_SA_LO

CPSW CPGMAC_SL1 Source Address Low Register

0x4A10 0074

SL1_SA_HI

CPSW CPGMAC_SL1 Source Address High Register

0x4A10 0078

P1_SEND_PERCENT

CPSW Port 1 Transmit Queue Send Percentages

0x4A10 007C – 0x4A10 008C

–

Reserved

0x4A10 0090

P2_MAX_BLKS

CPSW Port 2 Maximum FIFO Blocks Register

0x4A10 0094

P2_BLK_CNT

CPSW Port 2 FIFO Block Usage Count (Read Only)

0x4A10 0098

P2_TX_IN_CTL

CPSW Port 2 Transmit FIFO Control

0x4A10 009C

P2_PORT_VLAN

CPSW Port 2 VLAN Register

0x4A10 00A0

P2_TX_PRI_MAP

CPSW Port 2 Tx Header Priority to Switch Priority Mapping Register

0x4A10 00A4

P2_TS_CTL

CPSW_3GF Port 2 Time Sync Control Register

0x4A10 00A8

P2_TS_SEQ_LTYPE

CPSW_3GF Port 2 Time Sync LTYPE (and SEQ_ID_OFFSET)

0x4A10 00AC

P2_TS_VLAN

CPSW_3GF Port 2 Time Sync VLAN2 and VLAN2 Register

0x4A10 00B0

SL2_SA_LO

CPSW CPGMAC_SL2 Source Address Low Register

0x4A10 00B4

SL2_SA_HI

CPSW CPGMAC_SL2 Source Address High Register

0x4A10 00B8

P2_SEND_PERCENT

CPSW Port 2 Transmit Queue Send Percentages

0x4A10 00BC – 0x4A10 00FC

–

Reserved

0x4A10 0100

TX_IDVER

CPDMA_REGS TX Identification and Version Register

0x4A10 0104

TX_CONTROL

CPDMA_REGS TX Control Register

0x4A10 0108

TX_TEARDOWN

CPDMA_REGS TX Teardown Register

0x4A10 010C

–

Reserved

0x4A10 0110

RX_IDVER

CPDMA_REGS RX Identification and Version Register

0x4A10 0114

RX_CONTROL

CPDMA_REGS RX Control Register

0x4A10 0118

RX_TEARDOWN

CPDMA_REGS RX Teardown Register

0x4A10 011C

SOFT_RESET

CPDMA_REGS Soft Reset Register

0x4A10 0120

DMACONTROL

CPDMA_REGS CPDMA Control Register

0x4A10 0124

DMASTATUS

CPDMA_REGS CPDMA Status Register

0x4A10 0128

RX_BUFFER_OFFSET

CPDMA_REGS Receive Buffer Offset

0x4A10 012C

EMCONTROL

CPDMA_REGS Emulation Control

0x4A10 0130

TX_PRI0_RATE

CPDMA_REGS Transmit (Ingress) Priority 0 Rate

0x4A10 0134

TX_PRI1_RATE

CPDMA_REGS Transmit (Ingress) Priority 1 Rate

0x4A10 0138

TX_PRI2_RATE

CPDMA_REGS Transmit (Ingress) Priority 2 Rate

0x4A10 013C

TX_PRI3_RATE

CPDMA_REGS Transmit (Ingress) Priority 3 Rate

0x4A10 0140

TX_PRI4_RATE

CPDMA_REGS Transmit (Ingress) Priority 4 Rate

0x4A10 0144

TX_PRI5_RATE

CPDMA_REGS Transmit (Ingress) Priority 5 Rate

0x4A10 0148

TX_PRI6_RATE

CPDMA_REGS Transmit (Ingress) Priority 6 Rate

0x4A10 014C

TX_PRI7_RATE

CPDMA_REGS Transmit (Ingress) Priority 7 Rate

224

Peripheral Information and Timings

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