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AM3874 Datasheet(PDF) 228 Page - Texas Instruments |
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AM3874 Datasheet(HTML) 228 Page - Texas Instruments |
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228 / 361 page  AM3874, AM3871 SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com Table 8-14. Ethernet MAC Switch Registers (continued) ARM/L3 MASTERS EMAC HEX ACRONYM REGISTER NAME ADDRESS RANGE 0x4A10 0654 – Reserved 0x4A10 0658 - 0x4A10 06FF – Reserved 0x4A10 0700 SL1_IDVER CPGMAC_SL1 ID/Version Register 0x4A10 0704 SL1_MACCONTROL CPGMAC_SL1 Mac Control Register 0x4A10 0708 SL1_MACSTATUS CPGMAC_SL1 Mac Status Register 0x4A10 070C SL1_SOFT_RESET CPGMAC_SL1 Soft Reset Register 0x4A10 0710 SL1_RX_MAXLEN CPGMAC_SL1 RX Maximum Length Register 0x4A10 0714 SL1_BOFFTEST CPGMAC_SL1 Backoff Test Register 0x4A10 0718 SL1_RX_PAUSE CPGMAC_SL1 Receive Pause Timer Register 0x4A10 071C SL1_TX_PAUSE CPGMAC_SL1 Transmit Pause Timer Register 0x4A10 0720 SL1_EMCONTROL CPGMAC_SL1 Emulation Control Register 0x4A10 0724 SL1_RX_PRI_MAP CPGMAC_SL1 Rx Pkt Priority to Header Priority Mapping Register 0x4A10 0728 - 0x4A10 073C – Reserved 0x4A10 0740 SL2_IDVER CPGMAC_SL2 ID/Version Register 0x4A10 0744 SL2_MACCONTROL CPGMAC_SL2 Mac Control Register 0x4A10 0748 SL2_MACSTATUS CPGMAC_SL2 Mac Status Register 0x4A10 074C SL2_SOFT_RESET CPGMAC_SL2 Soft Reset Register 0x4A10 0750 SL2_RX_MAXLEN CPGMAC_SL2 RX Maximum Length Register 0x4A10 0754 SL2_BOFFTEST CPGMAC_SL2 Backoff Test Register 0x4A10 0758 SL2_RX_PAUSE CPGMAC_SL2 Receive Pause Timer Register 0x4A10 075C SL2_TX_PAUSE CPGMAC_SL2 Transmit Pause Timer Register 0x4A10 0760 SL2_EMCONTROL CPGMAC_SL2 Emulation Control 0x4A10 0764 SL2_RX_PRI_MAP CPGMAC_SL2 Rx Pkt Priority to Header Priority Mapping Register 0x4A10 0768 - 0x4A10 07FF – Reserved 0x4A10 0800 - 0x4A10 08FF see Table 8-27 MDIO Registers 0x4A10 0900 IDVER Subsystem ID Version Register 0x4A10 0904 SOFT_RESET Subsystem Soft Reset Register 0x4A10 0908 CONTROL Subsystem Control Register 0x4A10 090C INT_CONTROL Subsystem Interrupt Control 0x4A10 0910 C0_RX_THRESH_EN Subsystem Core 0 Receive Threshold Int Enable Register 0x4A10 0914 C0_RX_EN Subsystem Core 0 Receive Interrupt Enable Register 0x4A10 0918 C0_TX_EN Subsystem Core 0 Transmit Interrupt Enable Register 0x4A10 091C C0_MISC_EN Subsystem Core 0 Misc Interrupt Enable Register 0x4A10 0920 C1_RX_THRESH_EN Subsystem Core 1 Receive Threshold Int Enable Register 0x4A10 0924 C1_RX_EN Subsystem Core 1 Receive Interrupt Enable Register 0x4A10 0928 C1_TX_EN Subsystem Core 1 Transmit Interrupt Enable Register 0x4A10 092C C1_MISC_EN Subsystem Core 1 Misc Interrupt Enable Register 0x4A10 0930 C2_RX_THRESH_EN Subsystem Core 2 Receive Threshold Int Enable Register 0x4A10 0934 C2_RX_EN Subsystem Core 2 Receive Interrupt Enable Register 0x4A10 0938 C2_TX_EN Subsystem Core 2 Transmit Interrupt Enable Register 0x4A10 093C C2_MISC_EN Subsystem Core 2 Misc Interrupt Enable Register 0x4A10 0940 C0_RX_THRESH_STAT Subsystem Core 0 Rx Threshold Masked Int Status Register 0x4A10 0944 C0_RX_STAT Subsystem Core 0 Rx Interrupt Masked Int Status Register 0x4A10 0948 C0_TX_STAT Subsystem Core 0 Tx Interrupt Masked Int Status Register 0x4A10 094C C0_MISC_STAT Subsystem Core 0 Misc Interrupt Masked Int Status Register 0x4A10 0950 C1_RX_THRESH_STAT Subsystem Core 1 Rx Threshold Masked Int Status Register 228 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
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