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AM3874 Datasheet(PDF) 232 Page - Texas Instruments |
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AM3874 Datasheet(HTML) 232 Page - Texas Instruments |
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232 / 361 page  RMREFCLK 1 2 RM − M MCRS RM RXD1 R RXD0, R DV, RXER (inputs) RMREFCLK (Input) 1 3 4 4 2 AM3874, AM3871 SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com 8.6.2.2 EMAC RMII Electrical Data/Timing Table 8-20. Timing Requirements for EMAC[x]_RMREFCLK - RMII Operation (see Figure 8-13) OPP100/120/166 NO. UNIT MIN MAX 1 tc(RMREFCLK) Cycle time, EMAC[x]_RMREFCLK 19.999 20.001 ns 2 tw(RMREFCLKH) Pulse duration, EMAC[x]_RMREFCLK high 7 13 ns 3 tw(RMREFCLKL) Pulse duration, EMAC[x]_RMREFCLK low 7 13 ns 4 tt(RMREFCLK) Transition time, EMAC[x]_RMREFCLK 3 ns Figure 8-13. RMREFCLK Timing RMII Operation Table 8-21. Timing Requirements for EMAC RMII Receive (see Figure 8-13) OPP100/120/166 NO. UNIT MIN MAX tsu(RMRXD-RMREFCLK) Setup time, receive selected signals valid before 1 tsu(RMCRSDV-RMREFCLK) 4 ns EMAC[x]_RMREFCLK tsu(RMRXER-RMREFCLK) th(RMREFCLK-RMRXD) Hold time, receive selected signals valid after 2 th(RMREFCLK-RMCRSDV) 2 ns EMAC[x]_RMREFCLK th(RMREFCLK-RMRXER) Figure 8-14. EMAC Receive Interface Timing RMII Operation Table 8-22. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10/100 Mbits/s (see Figure 8-15) OPP100/120/166 NO. PARAMETER UNIT MIN MAX Delay time, EMAC[x]_RMREFCLK high to EMAC[x]_RMTXD[x] 1 td(RMREFCLK-RMTXD) 2.5 13 ns valid Delay time, EMAC[x]_RMREFCLK high to EMAC[x]_RMTXEN 2 tdd(RMREFCLK-RMTXEN) 2.5 13 valid 232 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
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