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AM3874 Datasheet(PDF) 317 Page - Texas Instruments |
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AM3874 Datasheet(HTML) 317 Page - Texas Instruments |
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317 / 361 page  AM3874, AM3871 www.ti.com SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013 8.15 Multichannel Buffered Serial Port (McBSP) The McBSP provides these functions: • Full-duplex communication • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit • Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices • Supports TDM, I2S, and similar formats • External shift clock or an internal, programmable frequency shift clock for data transfer • 5KB Tx and Rx buffer • Supports three interrupt and two DMA requests. The McBSP module may support two types of data transfer at the system level: • The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge and captured on the same edge (one clock period later). • The half-cycle mode, for which one half clock period is used to transfer the data, generated on one edge and captured on the opposite edge (one half clock period later). Note that a new data is generated only every clock period, which secures the required hold time. The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be configured accordingly with the external peripheral (activation edge capability) and the type of data transfer required at the system level. For more detailed information on the McBSP peripheral, see the Multichannel Buffered Serial Port (McBSP) chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7). The following sections describe the timing characteristics for applications in normal mode (that is, the McBSP connected to one peripheral) and TDM applications in multipoint mode. 8.15.1 McBSP Peripheral Register Descriptions Table 8-80. McBSP Registers(1) HEX ADDRESS ACRONYM REGISTER NAME 0x4700 0000 REVNB Revision Number Register 0x4700 0010 SYSCONFIG_REG System Configuration Register 0x4700 0020 EOI End of Interrupt Register 0x4700 0024 IRQSTATUS_RAW Interrupt Status Raw Register 0x4700 0028 IRQSTATUS Interrupt Status Register 0x4700 002C IRQENABLE_SET Interrupt Enable Set Register 0x4700 0030 IRQENABLE_CLR Interrupt Enable Clear Register 0x4700 0034 DMARXENABLE_SET DMA Rx Enable Set Register 0x4700 0038 DMATXENABLE_SET DMA Tx Enable Set Register 0x4700 003C DMARXENABLE_CLR DMA Rx Enable Clear Register 0x4700 0040 DMATXENABLE_CLR DMA Tx Enable Clear Register 0x4700 0048 DMARXWAKE_EN DMA Rx Wake Enable Register 0x4700 004C DMATXWAKE_EN DMA Tx Wake Enable Register 0x4700 0100 DRR_REG McBSP data receive 0x4700 0108 DXR_REG McBSP data transmit 0x4700 0110 SPCR2_REG McBSP serial port control 2 0x4700 0114 SPCR1_REG McBSP serial port control 1 (1) Note that the McBSP registers are 32-bit aligned. Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 317 Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
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